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@@ -14,8 +14,8 @@
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#define AT91_SHDWC_H
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#define AT91_SHDWC_H
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#define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */
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#define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */
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-#define AT91_SHDW_SHDW (1 << 0) /* Processor Reset */
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-#define AT91_SHDW_KEY (0xff << 24) /* KEY Password */
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+#define AT91_SHDW_SHDW (1 << 0) /* Shut Down command */
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+#define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */
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#define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */
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#define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */
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#define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */
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#define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */
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