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@@ -51,7 +51,7 @@ module_param(inline_threshold, int, 0644);
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MODULE_PARM_DESC(inline_threshold, "inline vs dsgl threshold (default=128)");
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static int _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr,
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- u32 len, void *data, int wait)
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+ u32 len, dma_addr_t data, int wait)
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{
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struct sk_buff *skb;
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struct ulp_mem_io *req;
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@@ -88,7 +88,7 @@ static int _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr,
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sgl->cmd_nsge = cpu_to_be32(ULPTX_CMD(ULP_TX_SC_DSGL) |
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ULPTX_NSGE(1));
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sgl->len0 = cpu_to_be32(len);
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- sgl->addr0 = cpu_to_be64(virt_to_phys(data));
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+ sgl->addr0 = cpu_to_be64(data);
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ret = c4iw_ofld_send(rdev, skb);
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if (ret)
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@@ -178,6 +178,13 @@ int _c4iw_write_mem_dma(struct c4iw_rdev *rdev, u32 addr, u32 len, void *data)
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u32 remain = len;
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u32 dmalen;
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int ret = 0;
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+ dma_addr_t daddr;
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+ dma_addr_t save;
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+
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+ daddr = dma_map_single(&rdev->lldi.pdev->dev, data, len, DMA_TO_DEVICE);
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+ if (dma_mapping_error(&rdev->lldi.pdev->dev, daddr))
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+ return -1;
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+ save = daddr;
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while (remain > inline_threshold) {
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if (remain < T4_ULPTX_MAX_DMA) {
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@@ -188,16 +195,18 @@ int _c4iw_write_mem_dma(struct c4iw_rdev *rdev, u32 addr, u32 len, void *data)
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} else
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dmalen = T4_ULPTX_MAX_DMA;
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remain -= dmalen;
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- ret = _c4iw_write_mem_dma_aligned(rdev, addr, dmalen, data,
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+ ret = _c4iw_write_mem_dma_aligned(rdev, addr, dmalen, daddr,
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!remain);
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if (ret)
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goto out;
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addr += dmalen >> 5;
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data += dmalen;
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+ daddr += dmalen;
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}
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if (remain)
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ret = _c4iw_write_mem_inline(rdev, addr, remain, data);
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out:
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+ dma_unmap_single(&rdev->lldi.pdev->dev, save, len, DMA_TO_DEVICE);
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return ret;
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}
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@@ -209,9 +218,17 @@ static int write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len,
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void *data)
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{
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if (is_t5(rdev->lldi.adapter_type) && use_dsgl) {
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- if (len > inline_threshold)
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- return _c4iw_write_mem_dma(rdev, addr, len, data);
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- else
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+ if (len > inline_threshold) {
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+ if (_c4iw_write_mem_dma(rdev, addr, len, data)) {
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+ printk_ratelimited(KERN_WARNING
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+ "%s: dma map"
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+ " failure (non fatal)\n",
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+ pci_name(rdev->lldi.pdev));
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+ return _c4iw_write_mem_inline(rdev, addr, len,
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+ data);
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+ } else
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+ return 0;
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+ } else
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return _c4iw_write_mem_inline(rdev, addr, len, data);
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} else
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return _c4iw_write_mem_inline(rdev, addr, len, data);
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