powerpc/dts: fix sRIO error interrupt for b4860 · 0e3d4373b8 - Gogs

powerpc/dts: fix sRIO error interrupt for b4860

For B4 platform, MPIC EISR register is in reversed bitmap order,
instead of "Error interrupt source 0-31. Bit 0 represents SRC0."
the correct ordering is "Error interrupt source 0-31. Bit 0
represents SRC31." This patch is to fix sRIO EISR bit value
of error interrupt in dts node.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>

Minghuan Lian 12 years ago

parent

682775b8de

commit

0e3d4373b8

1 changed files with 1 additions and 1 deletions

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							+ 1
							
							- 1
						
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
							 
								View File
							
				@@ -41,7 +41,7 @@
			
				 &rio {
			
				 	compatible = "fsl,srio";
			
				-	interrupts = <16 2 1 11>;
			
				+	interrupts = <16 2 1 20>;
			
				 	#address-cells = <2>;
			
				 	#size-cells = <2>;
			
				 	fsl,iommu-parent = <&pamu0>;