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+/* linux/arch/arm/plat-s5p/irq-eint.c
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+ *
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+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
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+ * http://www.samsung.com
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+ *
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+ * S5P - IRQ EINT support
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+*/
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+
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+#include <linux/kernel.h>
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+#include <linux/interrupt.h>
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+#include <linux/irq.h>
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+#include <linux/io.h>
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+#include <linux/sysdev.h>
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+#include <linux/gpio.h>
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+
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+#include <asm/hardware/vic.h>
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+
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+#include <plat/regs-irqtype.h>
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+
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+#include <mach/map.h>
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+#include <plat/cpu.h>
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+#include <plat/pm.h>
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+
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+#include <plat/gpio-cfg.h>
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+#include <mach/regs-gpio.h>
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+
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+static inline void s5p_irq_eint_mask(unsigned int irq)
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+{
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+ u32 mask;
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+
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+ mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
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+ mask |= eint_irq_to_bit(irq);
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+ __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
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+}
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+
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+static void s5p_irq_eint_unmask(unsigned int irq)
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+{
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+ u32 mask;
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+
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+ mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
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+ mask &= ~(eint_irq_to_bit(irq));
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+ __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
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+}
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+
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+static inline void s5p_irq_eint_ack(unsigned int irq)
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+{
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+ __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq)));
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+}
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+
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+static void s5p_irq_eint_maskack(unsigned int irq)
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+{
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+ /* compiler should in-line these */
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+ s5p_irq_eint_mask(irq);
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+ s5p_irq_eint_ack(irq);
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+}
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+
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+static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type)
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+{
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+ int offs = eint_offset(irq);
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+ int shift;
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+ u32 ctrl, mask;
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+ u32 newvalue = 0;
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+
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+ switch (type) {
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+ case IRQ_TYPE_EDGE_RISING:
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+ newvalue = S5P_EXTINT_RISEEDGE;
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+ break;
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+
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+ case IRQ_TYPE_EDGE_FALLING:
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+ newvalue = S5P_EXTINT_RISEEDGE;
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+ break;
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+
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+ case IRQ_TYPE_EDGE_BOTH:
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+ newvalue = S5P_EXTINT_BOTHEDGE;
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+ break;
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+
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+ case IRQ_TYPE_LEVEL_LOW:
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+ newvalue = S5P_EXTINT_LOWLEV;
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+ break;
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+
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+ case IRQ_TYPE_LEVEL_HIGH:
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+ newvalue = S5P_EXTINT_HILEV;
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+ break;
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+
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+ default:
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+ printk(KERN_ERR "No such irq type %d", type);
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+ return -EINVAL;
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+ }
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+
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+ shift = (offs & 0x7) * 4;
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+ mask = 0x7 << shift;
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+
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+ ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq)));
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+ ctrl &= ~mask;
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+ ctrl |= newvalue << shift;
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+ __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq)));
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+
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+ if ((0 <= offs) && (offs < 8))
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+ s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
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+
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+ else if ((8 <= offs) && (offs < 16))
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+ s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
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+
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+ else if ((16 <= offs) && (offs < 24))
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+ s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
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+
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+ else if ((24 <= offs) && (offs < 32))
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+ s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
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+
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+ else
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+ printk(KERN_ERR "No such irq number %d", offs);
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+
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+ return 0;
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+}
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+
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+static struct irq_chip s5p_irq_eint = {
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+ .name = "s5p-eint",
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+ .mask = s5p_irq_eint_mask,
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+ .unmask = s5p_irq_eint_unmask,
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+ .mask_ack = s5p_irq_eint_maskack,
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+ .ack = s5p_irq_eint_ack,
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+ .set_type = s5p_irq_eint_set_type,
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+#ifdef CONFIG_PM
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+ .set_wake = s3c_irqext_wake,
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+#endif
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+};
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+
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+/* s5p_irq_demux_eint
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+ *
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+ * This function demuxes the IRQ from the group0 external interrupts,
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+ * from EINTs 16 to 31. It is designed to be inlined into the specific
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+ * handler s5p_irq_demux_eintX_Y.
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+ *
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+ * Each EINT pend/mask registers handle eight of them.
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+ */
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+static inline void s5p_irq_demux_eint(unsigned int start)
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+{
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+ u32 status;
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+ u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
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+ unsigned int irq;
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+
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+ status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
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+ status &= ~mask;
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+ status &= 0xff;
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+
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+ while (status) {
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+ irq = fls(status);
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+ generic_handle_irq(irq - 1 + start);
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+ status &= ~(1 << irq);
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+ }
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+}
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+
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+static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
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+{
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+ s5p_irq_demux_eint(IRQ_EINT(16));
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+ s5p_irq_demux_eint(IRQ_EINT(24));
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+}
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+
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+static inline void s5p_irq_vic_eint_mask(unsigned int irq)
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+{
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+ s5p_irq_eint_mask(irq);
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+}
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+
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+static void s5p_irq_vic_eint_unmask(unsigned int irq)
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+{
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+ s5p_irq_eint_unmask(irq);
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+}
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+
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+static inline void s5p_irq_vic_eint_ack(unsigned int irq)
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+{
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+ __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq)));
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+}
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+
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+static void s5p_irq_vic_eint_maskack(unsigned int irq)
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+{
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+ s5p_irq_vic_eint_mask(irq);
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+ s5p_irq_vic_eint_ack(irq);
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+}
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+
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+static struct irq_chip s5p_irq_vic_eint = {
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+ .name = "s5p_vic_eint",
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+ .mask = s5p_irq_vic_eint_mask,
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+ .unmask = s5p_irq_vic_eint_unmask,
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+ .mask_ack = s5p_irq_vic_eint_maskack,
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+ .ack = s5p_irq_vic_eint_ack,
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+ .set_type = s5p_irq_eint_set_type,
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+#ifdef CONFIG_PM
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+ .set_wake = s3c_irqext_wake,
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+#endif
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+};
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+
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+int __init s5p_init_irq_eint(void)
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+{
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+ int irq;
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+
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+ for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
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+ set_irq_chip(irq, &s5p_irq_vic_eint);
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+
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+ for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
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+ set_irq_chip(irq, &s5p_irq_eint);
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+ set_irq_handler(irq, handle_level_irq);
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+ set_irq_flags(irq, IRQF_VALID);
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+ }
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+
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+ set_irq_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
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+ return 0;
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+}
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+
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+arch_initcall(s5p_init_irq_eint);
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Jongpill Lee