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@@ -276,6 +276,7 @@ static int i915_suspend(struct drm_device *dev)
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dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
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}
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i915_save_palette(dev, PIPE_A);
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+ dev_priv->savePIPEASTAT = I915_READ(I915REG_PIPEASTAT);
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/* Pipe & plane B info */
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dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
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@@ -303,6 +304,7 @@ static int i915_suspend(struct drm_device *dev)
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dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
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}
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i915_save_palette(dev, PIPE_B);
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+ dev_priv->savePIPEBSTAT = I915_READ(I915REG_PIPEBSTAT);
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/* CRT state */
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dev_priv->saveADPA = I915_READ(ADPA);
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@@ -329,6 +331,11 @@ static int i915_suspend(struct drm_device *dev)
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dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
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dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
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+ /* Interrupt state */
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+ dev_priv->saveIIR = I915_READ(I915REG_INT_IDENTITY_R);
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+ dev_priv->saveIER = I915_READ(I915REG_INT_ENABLE_R);
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+ dev_priv->saveIMR = I915_READ(I915REG_INT_MASK_R);
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+
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/* VGA state */
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dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
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dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
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