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@@ -27,6 +27,7 @@
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#include "sdhci-pltfm.h"
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#include "sdhci-esdhc.h"
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+#define SDHCI_CTRL_D3CD 0x08
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/* VENDOR SPEC register */
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#define SDHCI_VENDOR_SPEC 0xC0
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#define SDHCI_VENDOR_SPEC_SDIO_QUIRK 0x00000002
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@@ -141,13 +142,32 @@ static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct pltfm_imx_data *imx_data = pltfm_host->priv;
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struct esdhc_platform_data *boarddata = &imx_data->boarddata;
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-
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- if (unlikely((reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)
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- && (boarddata->cd_type == ESDHC_CD_GPIO)))
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- /*
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- * these interrupts won't work with a custom card_detect gpio
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- */
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- val &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
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+ u32 data;
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+
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+ if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
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+ if (boarddata->cd_type == ESDHC_CD_GPIO)
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+ /*
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+ * These interrupts won't work with a custom
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+ * card_detect gpio (only applied to mx25/35)
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+ */
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+ val &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
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+
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+ if (val & SDHCI_INT_CARD_INT) {
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+ /*
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+ * Clear and then set D3CD bit to avoid missing the
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+ * card interrupt. This is a eSDHC controller problem
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+ * so we need to apply the following workaround: clear
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+ * and set D3CD bit will make eSDHC re-sample the card
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+ * interrupt. In case a card interrupt was lost,
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+ * re-sample it by the following steps.
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+ */
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+ data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
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+ data &= ~SDHCI_CTRL_D3CD;
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+ writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
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+ data |= SDHCI_CTRL_D3CD;
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+ writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
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+ }
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+ }
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if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
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&& (reg == SDHCI_INT_STATUS)
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@@ -217,8 +237,10 @@ static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
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*/
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return;
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case SDHCI_HOST_CONTROL:
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- /* FSL messed up here, so we can just keep those two */
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- new_val = val & (SDHCI_CTRL_LED | SDHCI_CTRL_4BITBUS);
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+ /* FSL messed up here, so we can just keep those three */
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+ new_val = val & (SDHCI_CTRL_LED | \
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+ SDHCI_CTRL_4BITBUS | \
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+ SDHCI_CTRL_D3CD);
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/* ensure the endianess */
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new_val |= ESDHC_HOST_CONTROL_LE;
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/* DMA mode bits are shifted */
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