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@@ -5410,7 +5410,7 @@
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#define PCICFG_COMMAND_INT_DISABLE (1<<10)
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#define PCICFG_COMMAND_RESERVED (0x1f<<11)
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#define PCICFG_STATUS_OFFSET 0x06
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-#define PCICFG_REVESION_ID 0x08
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+#define PCICFG_REVESION_ID_OFFSET 0x08
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#define PCICFG_CACHE_LINE_SIZE 0x0c
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#define PCICFG_LATENCY_TIMER 0x0d
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#define PCICFG_BAR_1_LOW 0x10
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@@ -5438,7 +5438,7 @@
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#define PCICFG_PM_CSR_STATE (0x3<<0)
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#define PCICFG_PM_CSR_PME_ENABLE (1<<8)
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#define PCICFG_PM_CSR_PME_STATUS (1<<15)
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-#define PCICFG_MSI_CAP_ID 0x58
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+#define PCICFG_MSI_CAP_ID_OFFSET 0x58
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#define PCICFG_MSI_CONTROL_ENABLE (0x1<<16)
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#define PCICFG_MSI_CONTROL_MCAP (0x7<<17)
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#define PCICFG_MSI_CONTROL_MENA (0x7<<20)
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@@ -5446,7 +5446,7 @@
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#define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24)
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#define PCICFG_GRC_ADDRESS 0x78
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#define PCICFG_GRC_DATA 0x80
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-#define PCICFG_MSIX_CAP_ID 0xa0
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+#define PCICFG_MSIX_CAP_ID_OFFSET 0xa0
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#define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16)
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#define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27)
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#define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30)
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