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@@ -11,7 +11,7 @@
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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- * this program; if not, write to the Free Software Foundation, Inc.,
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+ * this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Authors:
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@@ -40,8 +40,7 @@ struct cdv_intel_p2_t {
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int p2_slow, p2_fast;
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};
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-struct cdv_intel_clock_t
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-{
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+struct cdv_intel_clock_t {
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/* given values */
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int n;
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int m1, m2;
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@@ -117,17 +116,18 @@ static const struct cdv_intel_limit_t cdv_intel_limits[] = {
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};
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#define _wait_for(COND, MS, W) ({ \
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- unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
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- int ret__ = 0; \
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- while (! (COND)) { \
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- if (time_after(jiffies, timeout__)) { \
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- ret__ = -ETIMEDOUT; \
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- break; \
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- } \
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- if (W && !in_dbg_master()) msleep(W); \
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- } \
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- ret__; \
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-})
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+ unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
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+ int ret__ = 0; \
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+ while (!(COND)) { \
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+ if (time_after(jiffies, timeout__)) { \
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+ ret__ = -ETIMEDOUT; \
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+ break; \
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+ } \
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+ if (W && !in_dbg_master()) \
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+ msleep(W); \
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+ } \
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+ ret__; \
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+})
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#define wait_for(COND, MS) _wait_for(COND, MS, 1)
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@@ -237,7 +237,7 @@ cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
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ref_value = 0x68A701;
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cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value);
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-
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+
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/* We don't know what the other fields of these regs are, so
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* leave them in place.
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*/
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@@ -324,14 +324,13 @@ cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
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lane_value |= LANE_PLL_ENABLE;
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cdv_sb_write(dev, lane_reg, lane_value);
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- /* Program the Lane2/3 for HDMI C */
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+ /* Program the Lane2/3 for HDMI C */
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lane_reg = PSB_LANE2;
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cdv_sb_read(dev, lane_reg, &lane_value);
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lane_value &= ~(LANE_PLL_MASK);
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lane_value |= LANE_PLL_ENABLE;
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cdv_sb_write(dev, lane_reg, lane_value);
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-
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lane_reg = PSB_LANE3;
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cdv_sb_read(dev, lane_reg, &lane_value);
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lane_value &= ~(LANE_PLL_MASK);
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@@ -362,17 +361,18 @@ bool cdv_intel_pipe_has_type(struct drm_crtc *crtc, int type)
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return false;
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}
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-static const struct cdv_intel_limit_t *cdv_intel_limit(struct drm_crtc *crtc, int refclk)
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+static const struct cdv_intel_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
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+ int refclk)
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{
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const struct cdv_intel_limit_t *limit;
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if (cdv_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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/*
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- * Now only single-channel LVDS is supported on CDV. If it is
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- * incorrect, please add the dual-channel LVDS.
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- */
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+ * Now only single-channel LVDS is supported on CDV. If it is
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+ * incorrect, please add the dual-channel LVDS.
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+ */
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if (refclk == 96000)
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limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96];
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- else
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+ else
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limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100];
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} else {
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if (refclk == 27000)
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@@ -384,7 +384,7 @@ static const struct cdv_intel_limit_t *cdv_intel_limit(struct drm_crtc *crtc, in
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}
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/* m1 is reserved as 0 in CDV, n is a ring counter */
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-static void cdv_intel_clock(struct drm_device *dev,
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+static void cdv_intel_clock(struct drm_device *dev,
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int refclk, struct cdv_intel_clock_t *clock)
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{
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clock->m = clock->m2 + 2;
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@@ -448,19 +448,22 @@ static bool cdv_intel_find_best_PLL(struct drm_crtc *crtc, int target,
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memset(best_clock, 0, sizeof(*best_clock));
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clock.m1 = 0;
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- /* m1 is reserved as 0 in CDV, n is a ring counter. So skip the m1 loop */
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+ /* m1 is reserved as 0 in CDV, n is a ring counter.
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+ So skip the m1 loop */
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for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
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for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max;
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clock.m2++) {
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- for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max;
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- clock.p1++) {
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+ for (clock.p1 = limit->p1.min;
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+ clock.p1 <= limit->p1.max;
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+ clock.p1++) {
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int this_err;
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cdv_intel_clock(dev, refclk, &clock);
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- if (!cdv_intel_PLL_is_valid(crtc, limit, &clock))
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+ if (!cdv_intel_PLL_is_valid(crtc,
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+ limit, &clock))
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continue;
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-
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+
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this_err = abs(clock.dot - target);
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if (this_err < err) {
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*best_clock = clock;
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@@ -533,7 +536,7 @@ int cdv_intel_pipe_set_base(struct drm_crtc *crtc,
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REG_WRITE(dspcntr_reg, dspcntr);
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dev_dbg(dev->dev,
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- "Writing base %08lX %08lX %d %d\n", start, offset, x, y);
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+ "Writing base %08lX %08lX %d %d\n", start, offset, x, y);
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REG_WRITE(dspbase, offset);
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REG_READ(dspbase);
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@@ -808,7 +811,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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dpll |= DPLLB_MODE_LVDS;
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else
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dpll |= DPLLB_MODE_DAC_SERIAL;
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- //dpll |= (2 << 11);
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+ /* dpll |= (2 << 11); */
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/* setup pipeconf */
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pipeconf = REG_READ(pipeconf_reg);
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@@ -824,14 +827,12 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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dspcntr |= DISPLAY_PLANE_ENABLE;
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pipeconf |= PIPEACONF_ENABLE;
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- REG_WRITE(dpll_reg,
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- dpll | DPLL_VGA_MODE_DIS |
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- DPLL_SYNCLOCK_ENABLE);
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- REG_READ(dpll_reg);
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+ REG_WRITE(dpll_reg, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
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+ REG_READ(dpll_reg);
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cdv_dpll_set_clock_cdv(dev, crtc, &clock);
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- udelay(150);
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+ udelay(150);
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/* The LVDS pin pair needs to be on before the DPLLs are enabled.
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@@ -864,7 +865,6 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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dpll |= DPLL_VCO_ENABLE;
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-
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/* Disable the panel fitter if it was on our pipe */
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if (cdv_intel_panel_fitter_pipe(dev) == pipe)
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REG_WRITE(PFIT_CONTROL, 0);
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@@ -873,24 +873,19 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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drm_mode_debug_printmodeline(mode);
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REG_WRITE(dpll_reg,
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- (REG_READ(dpll_reg) & ~DPLL_LOCK) |
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- DPLL_VCO_ENABLE);
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- REG_READ(dpll_reg);
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+ (REG_READ(dpll_reg) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);
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+ REG_READ(dpll_reg);
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/* Wait for the clocks to stabilize. */
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- udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */
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-
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- if (!(REG_READ(dpll_reg) & DPLL_LOCK)) {
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- dev_err(dev->dev, "Failed to get DPLL lock\n");
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- return -EBUSY;
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- }
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-
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- {
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- int sdvo_pixel_multiply =
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- adjusted_mode->clock / mode->clock;
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- REG_WRITE(dpll_md_reg,
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- (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
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- ((sdvo_pixel_multiply -
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- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
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+ udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */
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+
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+ if (!(REG_READ(dpll_reg) & DPLL_LOCK)) {
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+ dev_err(dev->dev, "Failed to get DPLL lock\n");
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+ return -EBUSY;
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+ }
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+
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+ {
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+ int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
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+ REG_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
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}
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REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
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@@ -956,10 +951,10 @@ void cdv_intel_crtc_load_lut(struct drm_crtc *crtc)
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palreg = PALETTE_C;
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break;
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default:
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- dev_err(dev->dev, "Illegal Pipe Number. \n");
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+ dev_err(dev->dev, "Illegal Pipe Number.\n");
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return;
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}
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-
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+
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if (gma_power_begin(dev, false)) {
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for (i = 0; i < 256; i++) {
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REG_WRITE(palreg + 4 * i,
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@@ -1276,7 +1271,7 @@ static int cdv_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
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}
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static void cdv_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
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- u16 *green, u16 *blue, uint32_t start, uint32_t size)
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+ u16 *green, u16 *blue, uint32_t start, uint32_t size)
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{
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struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
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int i;
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@@ -1294,10 +1289,10 @@ static void cdv_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
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static int cdv_crtc_set_config(struct drm_mode_set *set)
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{
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int ret = 0;
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- struct drm_device * dev = set->crtc->dev;
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- struct drm_psb_private * dev_priv = dev->dev_private;
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+ struct drm_device *dev = set->crtc->dev;
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+ struct drm_psb_private *dev_priv = dev->dev_private;
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- if(!dev_priv->rpm_enabled)
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+ if (!dev_priv->rpm_enabled)
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return drm_crtc_helper_set_config(set);
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pm_runtime_forbid(&dev->pdev->dev);
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@@ -1489,7 +1484,7 @@ void cdv_intel_cursor_init(struct drm_device *dev, int pipe)
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{
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uint32_t control;
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uint32_t base;
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-
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+
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switch (pipe) {
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case 0:
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control = CURACNTR;
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