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@@ -275,16 +275,9 @@ int pciehp_check_link_status(struct controller *ctrl)
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* hot-plug capable downstream port. But old controller might
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* not implement it. In this case, we wait for 1000 ms.
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*/
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- if (ctrl->link_active_reporting){
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- /* Wait for Data Link Layer Link Active bit to be set */
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+ if (ctrl->link_active_reporting)
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pcie_wait_link_active(ctrl);
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- /*
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- * We must wait for 100 ms after the Data Link Layer
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- * Link Active bit reads 1b before initiating a
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- * configuration access to the hot added device.
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- */
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- msleep(100);
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- } else
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+ else
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msleep(1000);
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retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
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