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@@ -36,7 +36,7 @@
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#include <linux/of_address.h>
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#include <asm/irq.h>
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-
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+#include <asm/exception.h>
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#define VT8500_ICPC_IRQ 0x20
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#define VT8500_ICPC_FIQ 0x24
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@@ -66,30 +66,34 @@
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#define VT8500_EDGE ( VT8500_TRIGGER_RISING \
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| VT8500_TRIGGER_FALLING)
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-static int irq_cnt;
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+/* vt8500 has 1 intc, wm8505 and wm8650 have 2 */
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+#define VT8500_INTC_MAX 2
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-struct vt8500_irq_priv {
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- void __iomem *base;
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+struct vt8500_irq_data {
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+ void __iomem *base; /* IO Memory base address */
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+ struct irq_domain *domain; /* Domain for this controller */
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};
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+/* Global variable for accessing io-mem addresses */
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+static struct vt8500_irq_data intc[VT8500_INTC_MAX];
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+static u32 active_cnt = 0;
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+
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static void vt8500_irq_mask(struct irq_data *d)
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{
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- struct vt8500_irq_priv *priv =
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- (struct vt8500_irq_priv *)(d->domain->host_data);
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+ struct vt8500_irq_data *priv = d->domain->host_data;
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void __iomem *base = priv->base;
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- u8 edge;
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+ void __iomem *stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4);
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+ u8 edge, dctr;
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+ u32 status;
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edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE;
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if (edge) {
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- void __iomem *stat_reg = base + VT8500_ICIS
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- + (d->hwirq < 32 ? 0 : 4);
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- unsigned status = readl(stat_reg);
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+ status = readl(stat_reg);
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status |= (1 << (d->hwirq & 0x1f));
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writel(status, stat_reg);
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} else {
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- u8 dctr = readb(base + VT8500_ICDC + d->hwirq);
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-
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+ dctr = readb(base + VT8500_ICDC + d->hwirq);
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dctr &= ~VT8500_INT_ENABLE;
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writeb(dctr, base + VT8500_ICDC + d->hwirq);
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}
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@@ -97,8 +101,7 @@ static void vt8500_irq_mask(struct irq_data *d)
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static void vt8500_irq_unmask(struct irq_data *d)
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{
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- struct vt8500_irq_priv *priv =
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- (struct vt8500_irq_priv *)(d->domain->host_data);
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+ struct vt8500_irq_data *priv = d->domain->host_data;
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void __iomem *base = priv->base;
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u8 dctr;
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@@ -109,8 +112,7 @@ static void vt8500_irq_unmask(struct irq_data *d)
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static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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- struct vt8500_irq_priv *priv =
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- (struct vt8500_irq_priv *)(d->domain->host_data);
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+ struct vt8500_irq_data *priv = d->domain->host_data;
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void __iomem *base = priv->base;
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u8 dctr;
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@@ -148,17 +150,15 @@ static struct irq_chip vt8500_irq_chip = {
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static void __init vt8500_init_irq_hw(void __iomem *base)
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{
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- unsigned int i;
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+ u32 i;
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/* Enable rotating priority for IRQ */
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writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
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writel(0x00, base + VT8500_ICPC_FIQ);
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- for (i = 0; i < 64; i++) {
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- /* Disable all interrupts and route them to IRQ */
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- writeb(VT8500_INT_DISABLE | ICDC_IRQ,
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- base + VT8500_ICDC + i);
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- }
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+ /* Disable all interrupts and route them to IRQ */
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+ for (i = 0; i < 64; i++)
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+ writeb(VT8500_INT_DISABLE | ICDC_IRQ, base + VT8500_ICDC + i);
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}
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static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
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@@ -175,33 +175,67 @@ static struct irq_domain_ops vt8500_irq_domain_ops = {
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.xlate = irq_domain_xlate_onecell,
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};
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+asmlinkage void __exception_irq_entry vt8500_handle_irq(struct pt_regs *regs)
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+{
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+ u32 stat, i;
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+ int irqnr, virq;
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+ void __iomem *base;
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+
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+ /* Loop through each active controller */
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+ for (i=0; i<active_cnt; i++) {
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+ base = intc[i].base;
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+ irqnr = readl_relaxed(base) & 0x3F;
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+ /*
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+ Highest Priority register default = 63, so check that this
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+ is a real interrupt by checking the status register
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+ */
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+ if (irqnr == 63) {
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+ stat = readl_relaxed(base + VT8500_ICIS + 4);
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+ if (!(stat & BIT(31)))
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+ continue;
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+ }
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+
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+ virq = irq_find_mapping(intc[i].domain, irqnr);
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+ handle_IRQ(virq, regs);
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+ }
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+}
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+
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int __init vt8500_irq_init(struct device_node *node, struct device_node *parent)
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{
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- struct irq_domain *vt8500_irq_domain;
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- struct vt8500_irq_priv *priv;
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int irq, i;
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struct device_node *np = node;
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- priv = kzalloc(sizeof(struct vt8500_irq_priv), GFP_KERNEL);
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- priv->base = of_iomap(np, 0);
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+ if (active_cnt == VT8500_INTC_MAX) {
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+ pr_err("%s: Interrupt controllers > VT8500_INTC_MAX\n",
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+ __func__);
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+ goto out;
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+ }
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+
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+ intc[active_cnt].base = of_iomap(np, 0);
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+ intc[active_cnt].domain = irq_domain_add_linear(node, 64,
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+ &vt8500_irq_domain_ops, &intc[active_cnt]);
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- vt8500_irq_domain = irq_domain_add_legacy(node, 64, irq_cnt, 0,
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- &vt8500_irq_domain_ops, priv);
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- if (!vt8500_irq_domain)
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- pr_err("%s: Unable to add wmt irq domain!\n", __func__);
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+ if (!intc[active_cnt].base) {
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+ pr_err("%s: Unable to map IO memory\n", __func__);
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+ goto out;
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+ }
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+
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+ if (!intc[active_cnt].domain) {
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+ pr_err("%s: Unable to add irq domain!\n", __func__);
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+ goto out;
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+ }
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- irq_set_default_host(vt8500_irq_domain);
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+ vt8500_init_irq_hw(intc[active_cnt].base);
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- vt8500_init_irq_hw(priv->base);
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+ pr_info("vt8500-irq: Added interrupt controller\n");
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- pr_info("Added IRQ Controller @ %x [virq_base = %d]\n",
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- (u32)(priv->base), irq_cnt);
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+ active_cnt++;
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/* check if this is a slaved controller */
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if (of_irq_count(np) != 0) {
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/* check that we have the correct number of interrupts */
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if (of_irq_count(np) != 8) {
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- pr_err("%s: Incorrect IRQ map for slave controller\n",
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+ pr_err("%s: Incorrect IRQ map for slaved controller\n",
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__func__);
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return -EINVAL;
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}
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@@ -213,9 +247,7 @@ int __init vt8500_irq_init(struct device_node *node, struct device_node *parent)
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pr_info("vt8500-irq: Enabled slave->parent interrupts\n");
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}
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-
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- irq_cnt += 64;
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-
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+out:
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return 0;
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}
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