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@@ -107,7 +107,7 @@
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/*
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/*
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* INT_SOURCE_CSR: Interrupt source register.
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* INT_SOURCE_CSR: Interrupt source register.
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* Write one to clear corresponding bit.
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* Write one to clear corresponding bit.
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- * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
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+ * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO
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*/
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*/
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#define INT_SOURCE_CSR 0x0200
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#define INT_SOURCE_CSR 0x0200
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#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
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#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
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