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@@ -292,7 +292,7 @@ int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
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{
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struct ipu_dmfc_priv *priv = dmfc->priv;
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int slots = dmfc_bandwidth_to_slots(priv, bandwidth_pixel_per_second);
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- int segment = 0, ret = 0;
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+ int segment = -1, ret = 0;
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dev_dbg(priv->dev, "dmfc: trying to allocate %ldMpixel/s for IPU channel %d\n",
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bandwidth_pixel_per_second / 1000000,
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@@ -307,7 +307,17 @@ int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
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goto out;
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}
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- segment = dmfc_find_slots(priv, slots);
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+ /* Always allocate at least 128*4 bytes (2 slots) */
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+ if (slots < 2)
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+ slots = 2;
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+
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+ /* For the MEM_BG channel, first try to allocate twice the slots */
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+ if (dmfc->data->ipu_channel == IPUV3_CHANNEL_MEM_BG_SYNC)
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+ segment = dmfc_find_slots(priv, slots * 2);
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+ if (segment >= 0)
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+ slots *= 2;
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+ else
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+ segment = dmfc_find_slots(priv, slots);
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if (segment < 0) {
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ret = -EBUSY;
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goto out;
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@@ -391,7 +401,7 @@ int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
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* We have a total bandwidth of clkrate * 4pixel divided
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* into 8 slots.
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*/
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- priv->bandwidth_per_slot = clk_get_rate(ipu_clk) / 8;
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+ priv->bandwidth_per_slot = clk_get_rate(ipu_clk) * 4 / 8;
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dev_dbg(dev, "dmfc: 8 slots with %ldMpixel/s bandwidth each\n",
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priv->bandwidth_per_slot / 1000000);
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