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@@ -82,31 +82,6 @@
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#define SLOT_100MHZ_PCIX_533 0x0f000000
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#define SLOT_100MHZ_PCIX_533 0x0f000000
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#define SLOT_133MHZ_PCIX_533 0xf0000000
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#define SLOT_133MHZ_PCIX_533 0xf0000000
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-
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-/* Secondary Bus Configuration Register */
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-/* For PI = 1, Bits 0 to 2 have been encoded as follows to show current bus speed/mode */
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-#define PCI_33MHZ 0x0
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-#define PCI_66MHZ 0x1
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-#define PCIX_66MHZ 0x2
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-#define PCIX_100MHZ 0x3
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-#define PCIX_133MHZ 0x4
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-
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-/* For PI = 2, Bits 0 to 3 have been encoded as follows to show current bus speed/mode */
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-#define PCI_33MHZ 0x0
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-#define PCI_66MHZ 0x1
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-#define PCIX_66MHZ 0x2
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-#define PCIX_100MHZ 0x3
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-#define PCIX_133MHZ 0x4
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-#define PCIX_66MHZ_ECC 0x5
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-#define PCIX_100MHZ_ECC 0x6
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-#define PCIX_133MHZ_ECC 0x7
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-#define PCIX_66MHZ_266 0x9
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-#define PCIX_100MHZ_266 0xa
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-#define PCIX_133MHZ_266 0xb
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-#define PCIX_66MHZ_533 0x11
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-#define PCIX_100MHZ_533 0x12
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-#define PCIX_133MHZ_533 0x13
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-
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/* Slot Configuration */
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/* Slot Configuration */
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#define SLOT_NUM 0x0000001F
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#define SLOT_NUM 0x0000001F
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#define FIRST_DEV_NUM 0x00001F00
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#define FIRST_DEV_NUM 0x00001F00
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@@ -548,81 +523,41 @@ static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
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static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
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static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
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{
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{
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- struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
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- u32 slot_reg;
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- u16 slot_status, sec_bus_status;
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- u8 m66_cap, pcix_cap, pi;
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int retval = 0;
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int retval = 0;
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+ struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
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+ u32 slot_reg = readl(php_ctlr->creg + SLOT1 + 4 * slot->hp_slot);
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+ u8 pcix_cap = (slot_reg >> 12) & 7;
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+ u8 m66_cap = (slot_reg >> 9) & 1;
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DBG_ENTER_ROUTINE
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DBG_ENTER_ROUTINE
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- if (!slot->ctrl->hpc_ctlr_handle) {
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- err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
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- return -1;
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- }
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-
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- if (slot->hp_slot >= php_ctlr->num_slots) {
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- err("%s: Invalid HPC slot number!\n", __FUNCTION__);
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- return -1;
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- }
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-
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- pi = readb(php_ctlr->creg + PROG_INTERFACE);
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- slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
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- dbg("%s: pi = %d, slot_reg = %x\n", __FUNCTION__, pi, slot_reg);
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- slot_status = (u16) slot_reg;
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- dbg("%s: slot_status = %x\n", __FUNCTION__, slot_status);
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- sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG);
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-
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- pcix_cap = (u8) ((slot_status & 0x3000) >> 12);
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- dbg("%s: pcix_cap = %x\n", __FUNCTION__, pcix_cap);
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- m66_cap = (u8) ((slot_status & 0x0200) >> 9);
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- dbg("%s: m66_cap = %x\n", __FUNCTION__, m66_cap);
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+ dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
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+ __FUNCTION__, slot_reg, pcix_cap, m66_cap);
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-
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- if (pi == 2) {
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- switch (pcix_cap) {
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- case 0:
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- *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
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- break;
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- case 1:
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- *value = PCI_SPEED_66MHz_PCIX;
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- break;
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- case 3:
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- *value = PCI_SPEED_133MHz_PCIX;
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- break;
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- case 4:
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- *value = PCI_SPEED_133MHz_PCIX_266;
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- break;
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- case 5:
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- *value = PCI_SPEED_133MHz_PCIX_533;
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- break;
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- case 2: /* Reserved */
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- default:
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- *value = PCI_SPEED_UNKNOWN;
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- retval = -ENODEV;
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- break;
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- }
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- } else {
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- switch (pcix_cap) {
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- case 0:
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- *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
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- break;
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- case 1:
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- *value = PCI_SPEED_66MHz_PCIX;
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- break;
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- case 3:
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- *value = PCI_SPEED_133MHz_PCIX;
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- break;
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- case 2: /* Reserved */
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- default:
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- *value = PCI_SPEED_UNKNOWN;
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- retval = -ENODEV;
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- break;
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- }
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+ switch (pcix_cap) {
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+ case 0x0:
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+ *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
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+ break;
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+ case 0x1:
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+ *value = PCI_SPEED_66MHz_PCIX;
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+ break;
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+ case 0x3:
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+ *value = PCI_SPEED_133MHz_PCIX;
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+ break;
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+ case 0x4:
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+ *value = PCI_SPEED_133MHz_PCIX_266;
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+ break;
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+ case 0x5:
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+ *value = PCI_SPEED_133MHz_PCIX_533;
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+ break;
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+ case 0x2:
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+ default:
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+ *value = PCI_SPEED_UNKNOWN;
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+ retval = -ENODEV;
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+ break;
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}
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}
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dbg("Adapter speed = %d\n", *value);
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dbg("Adapter speed = %d\n", *value);
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-
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DBG_LEAVE_ROUTINE
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DBG_LEAVE_ROUTINE
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return retval;
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return retval;
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}
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}
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@@ -965,98 +900,66 @@ static int hpc_slot_disable(struct slot * slot)
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static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
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static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
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{
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{
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- u8 slot_cmd;
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- u8 pi;
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- int retval = 0;
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+ int retval;
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struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
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struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
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+ u8 pi, cmd;
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DBG_ENTER_ROUTINE
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DBG_ENTER_ROUTINE
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-
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- if (!slot->ctrl->hpc_ctlr_handle) {
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- err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
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- return -1;
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- }
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pi = readb(php_ctlr->creg + PROG_INTERFACE);
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pi = readb(php_ctlr->creg + PROG_INTERFACE);
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-
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- if (pi == 1) {
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- switch (value) {
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- case 0:
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- slot_cmd = SETA_PCI_33MHZ;
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- break;
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- case 1:
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- slot_cmd = SETA_PCI_66MHZ;
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- break;
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- case 2:
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- slot_cmd = SETA_PCIX_66MHZ;
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- break;
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- case 3:
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- slot_cmd = SETA_PCIX_100MHZ;
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- break;
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- case 4:
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- slot_cmd = SETA_PCIX_133MHZ;
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- break;
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- default:
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- slot_cmd = PCI_SPEED_UNKNOWN;
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- retval = -ENODEV;
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- return retval;
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- }
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- } else {
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- switch (value) {
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- case 0:
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- slot_cmd = SETB_PCI_33MHZ;
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- break;
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- case 1:
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- slot_cmd = SETB_PCI_66MHZ;
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- break;
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- case 2:
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- slot_cmd = SETB_PCIX_66MHZ_PM;
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- break;
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- case 3:
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- slot_cmd = SETB_PCIX_100MHZ_PM;
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- break;
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- case 4:
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- slot_cmd = SETB_PCIX_133MHZ_PM;
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- break;
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- case 5:
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- slot_cmd = SETB_PCIX_66MHZ_EM;
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- break;
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- case 6:
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- slot_cmd = SETB_PCIX_100MHZ_EM;
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- break;
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- case 7:
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- slot_cmd = SETB_PCIX_133MHZ_EM;
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- break;
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- case 8:
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- slot_cmd = SETB_PCIX_66MHZ_266;
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- break;
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- case 0x9:
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- slot_cmd = SETB_PCIX_100MHZ_266;
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- break;
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- case 0xa:
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- slot_cmd = SETB_PCIX_133MHZ_266;
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- break;
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- case 0xb:
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- slot_cmd = SETB_PCIX_66MHZ_533;
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- break;
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- case 0xc:
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- slot_cmd = SETB_PCIX_100MHZ_533;
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- break;
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- case 0xd:
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- slot_cmd = SETB_PCIX_133MHZ_533;
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- break;
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- default:
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- slot_cmd = PCI_SPEED_UNKNOWN;
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- retval = -ENODEV;
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- return retval;
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- }
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+ if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))
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+ return -EINVAL;
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+ switch (value) {
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+ case PCI_SPEED_33MHz:
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+ cmd = SETA_PCI_33MHZ;
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+ break;
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+ case PCI_SPEED_66MHz:
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+ cmd = SETA_PCI_66MHZ;
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+ break;
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+ case PCI_SPEED_66MHz_PCIX:
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+ cmd = SETA_PCIX_66MHZ;
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+ break;
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+ case PCI_SPEED_100MHz_PCIX:
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+ cmd = SETA_PCIX_100MHZ;
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+ break;
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+ case PCI_SPEED_133MHz_PCIX:
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+ cmd = SETA_PCIX_133MHZ;
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+ break;
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+ case PCI_SPEED_66MHz_PCIX_ECC:
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+ cmd = SETB_PCIX_66MHZ_EM;
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+ break;
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+ case PCI_SPEED_100MHz_PCIX_ECC:
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+ cmd = SETB_PCIX_100MHZ_EM;
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+ break;
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+ case PCI_SPEED_133MHz_PCIX_ECC:
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+ cmd = SETB_PCIX_133MHZ_EM;
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+ break;
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+ case PCI_SPEED_66MHz_PCIX_266:
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+ cmd = SETB_PCIX_66MHZ_266;
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+ break;
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+ case PCI_SPEED_100MHz_PCIX_266:
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+ cmd = SETB_PCIX_100MHZ_266;
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+ break;
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+ case PCI_SPEED_133MHz_PCIX_266:
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+ cmd = SETB_PCIX_133MHZ_266;
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+ break;
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+ case PCI_SPEED_66MHz_PCIX_533:
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+ cmd = SETB_PCIX_66MHZ_533;
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+ break;
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+ case PCI_SPEED_100MHz_PCIX_533:
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+ cmd = SETB_PCIX_100MHZ_533;
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+ break;
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+ case PCI_SPEED_133MHz_PCIX_533:
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+ cmd = SETB_PCIX_133MHZ_533;
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+ break;
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+ default:
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+ return -EINVAL;
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}
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}
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- retval = shpc_write_cmd(slot, 0, slot_cmd);
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- if (retval) {
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+
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+ retval = shpc_write_cmd(slot, 0, cmd);
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+ if (retval)
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err("%s: Write command failed!\n", __FUNCTION__);
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err("%s: Write command failed!\n", __FUNCTION__);
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- return -1;
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- }
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DBG_LEAVE_ROUTINE
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DBG_LEAVE_ROUTINE
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return retval;
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return retval;
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@@ -1163,64 +1066,43 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
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static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
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static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
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{
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{
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+ int retval = 0;
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struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
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struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
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enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
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enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
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- int retval = 0;
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- u8 pi;
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- u32 slot_avail1, slot_avail2;
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+ u8 pi = readb(php_ctlr->creg + PROG_INTERFACE);
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+ u32 slot_avail1 = readl(php_ctlr->creg + SLOT_AVAIL1);
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+ u32 slot_avail2 = readl(php_ctlr->creg + SLOT_AVAIL2);
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DBG_ENTER_ROUTINE
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DBG_ENTER_ROUTINE
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- if (!slot->ctrl->hpc_ctlr_handle) {
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- err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
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- return -1;
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- }
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-
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- if (slot->hp_slot >= php_ctlr->num_slots) {
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- err("%s: Invalid HPC slot number!\n", __FUNCTION__);
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- return -1;
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- }
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-
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- pi = readb(php_ctlr->creg + PROG_INTERFACE);
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- slot_avail1 = readl(php_ctlr->creg + SLOT_AVAIL1);
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- slot_avail2 = readl(php_ctlr->creg + SLOT_AVAIL2);
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-
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if (pi == 2) {
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if (pi == 2) {
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if (slot_avail2 & SLOT_133MHZ_PCIX_533)
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if (slot_avail2 & SLOT_133MHZ_PCIX_533)
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- bus_speed = PCIX_133MHZ_533;
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+ bus_speed = PCI_SPEED_133MHz_PCIX_533;
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else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
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else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
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- bus_speed = PCIX_100MHZ_533;
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|
|
|
|
|
+ bus_speed = PCI_SPEED_100MHz_PCIX_533;
|
|
else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
|
|
else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
|
|
- bus_speed = PCIX_66MHZ_533;
|
|
|
|
|
|
+ bus_speed = PCI_SPEED_66MHz_PCIX_533;
|
|
else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
|
|
else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
|
|
- bus_speed = PCIX_133MHZ_266;
|
|
|
|
|
|
+ bus_speed = PCI_SPEED_133MHz_PCIX_266;
|
|
else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
|
|
else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
|
|
- bus_speed = PCIX_100MHZ_266;
|
|
|
|
|
|
+ bus_speed = PCI_SPEED_100MHz_PCIX_266;
|
|
else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
|
|
else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
|
|
- bus_speed = PCIX_66MHZ_266;
|
|
|
|
- else if (slot_avail1 & SLOT_133MHZ_PCIX)
|
|
|
|
- bus_speed = PCIX_133MHZ;
|
|
|
|
- else if (slot_avail1 & SLOT_100MHZ_PCIX)
|
|
|
|
- bus_speed = PCIX_100MHZ;
|
|
|
|
- else if (slot_avail1 & SLOT_66MHZ_PCIX)
|
|
|
|
- bus_speed = PCIX_66MHZ;
|
|
|
|
- else if (slot_avail2 & SLOT_66MHZ)
|
|
|
|
- bus_speed = PCI_66MHZ;
|
|
|
|
- else if (slot_avail1 & SLOT_33MHZ)
|
|
|
|
- bus_speed = PCI_33MHZ;
|
|
|
|
- else bus_speed = PCI_SPEED_UNKNOWN;
|
|
|
|
- } else {
|
|
|
|
|
|
+ bus_speed = PCI_SPEED_66MHz_PCIX_266;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ if (bus_speed == PCI_SPEED_UNKNOWN) {
|
|
if (slot_avail1 & SLOT_133MHZ_PCIX)
|
|
if (slot_avail1 & SLOT_133MHZ_PCIX)
|
|
- bus_speed = PCIX_133MHZ;
|
|
|
|
|
|
+ bus_speed = PCI_SPEED_133MHz_PCIX;
|
|
else if (slot_avail1 & SLOT_100MHZ_PCIX)
|
|
else if (slot_avail1 & SLOT_100MHZ_PCIX)
|
|
- bus_speed = PCIX_100MHZ;
|
|
|
|
|
|
+ bus_speed = PCI_SPEED_100MHz_PCIX;
|
|
else if (slot_avail1 & SLOT_66MHZ_PCIX)
|
|
else if (slot_avail1 & SLOT_66MHZ_PCIX)
|
|
- bus_speed = PCIX_66MHZ;
|
|
|
|
|
|
+ bus_speed = PCI_SPEED_66MHz_PCIX;
|
|
else if (slot_avail2 & SLOT_66MHZ)
|
|
else if (slot_avail2 & SLOT_66MHZ)
|
|
- bus_speed = PCI_66MHZ;
|
|
|
|
|
|
+ bus_speed = PCI_SPEED_66MHz;
|
|
else if (slot_avail1 & SLOT_33MHZ)
|
|
else if (slot_avail1 & SLOT_33MHZ)
|
|
- bus_speed = PCI_33MHZ;
|
|
|
|
- else bus_speed = PCI_SPEED_UNKNOWN;
|
|
|
|
|
|
+ bus_speed = PCI_SPEED_33MHz;
|
|
|
|
+ else
|
|
|
|
+ retval = -ENODEV;
|
|
}
|
|
}
|
|
|
|
|
|
*value = bus_speed;
|
|
*value = bus_speed;
|
|
@@ -1231,111 +1113,69 @@ static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
|
|
|
|
|
|
static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value)
|
|
static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value)
|
|
{
|
|
{
|
|
|
|
+ int retval = 0;
|
|
struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
|
|
struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
|
|
enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
|
|
enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
|
|
- u16 sec_bus_status;
|
|
|
|
- int retval = 0;
|
|
|
|
- u8 pi;
|
|
|
|
|
|
+ u16 sec_bus_reg = readw(php_ctlr->creg + SEC_BUS_CONFIG);
|
|
|
|
+ u8 pi = readb(php_ctlr->creg + PROG_INTERFACE);
|
|
|
|
+ u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);
|
|
|
|
|
|
DBG_ENTER_ROUTINE
|
|
DBG_ENTER_ROUTINE
|
|
|
|
|
|
- if (!slot->ctrl->hpc_ctlr_handle) {
|
|
|
|
- err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
|
|
|
|
- return -1;
|
|
|
|
- }
|
|
|
|
-
|
|
|
|
- if (slot->hp_slot >= php_ctlr->num_slots) {
|
|
|
|
- err("%s: Invalid HPC slot number!\n", __FUNCTION__);
|
|
|
|
- return -1;
|
|
|
|
|
|
+ if ((pi == 1) && (speed_mode > 4)) {
|
|
|
|
+ *value = PCI_SPEED_UNKNOWN;
|
|
|
|
+ return -ENODEV;
|
|
}
|
|
}
|
|
|
|
|
|
- pi = readb(php_ctlr->creg + PROG_INTERFACE);
|
|
|
|
- sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG);
|
|
|
|
-
|
|
|
|
- if (pi == 2) {
|
|
|
|
- switch (sec_bus_status & 0x000f) {
|
|
|
|
- case 0:
|
|
|
|
- bus_speed = PCI_SPEED_33MHz;
|
|
|
|
- break;
|
|
|
|
- case 1:
|
|
|
|
- bus_speed = PCI_SPEED_66MHz;
|
|
|
|
- break;
|
|
|
|
- case 2:
|
|
|
|
- bus_speed = PCI_SPEED_66MHz_PCIX;
|
|
|
|
- break;
|
|
|
|
- case 3:
|
|
|
|
- bus_speed = PCI_SPEED_100MHz_PCIX;
|
|
|
|
- break;
|
|
|
|
- case 4:
|
|
|
|
- bus_speed = PCI_SPEED_133MHz_PCIX;
|
|
|
|
- break;
|
|
|
|
- case 5:
|
|
|
|
- bus_speed = PCI_SPEED_66MHz_PCIX_ECC;
|
|
|
|
- break;
|
|
|
|
- case 6:
|
|
|
|
- bus_speed = PCI_SPEED_100MHz_PCIX_ECC;
|
|
|
|
- break;
|
|
|
|
- case 7:
|
|
|
|
- bus_speed = PCI_SPEED_133MHz_PCIX_ECC;
|
|
|
|
- break;
|
|
|
|
- case 8:
|
|
|
|
- bus_speed = PCI_SPEED_66MHz_PCIX_266;
|
|
|
|
- break;
|
|
|
|
- case 9:
|
|
|
|
- bus_speed = PCI_SPEED_100MHz_PCIX_266;
|
|
|
|
- break;
|
|
|
|
- case 0xa:
|
|
|
|
- bus_speed = PCI_SPEED_133MHz_PCIX_266;
|
|
|
|
- break;
|
|
|
|
- case 0xb:
|
|
|
|
- bus_speed = PCI_SPEED_66MHz_PCIX_533;
|
|
|
|
- break;
|
|
|
|
- case 0xc:
|
|
|
|
- bus_speed = PCI_SPEED_100MHz_PCIX_533;
|
|
|
|
- break;
|
|
|
|
- case 0xd:
|
|
|
|
- bus_speed = PCI_SPEED_133MHz_PCIX_533;
|
|
|
|
- break;
|
|
|
|
- case 0xe:
|
|
|
|
- case 0xf:
|
|
|
|
- default:
|
|
|
|
- bus_speed = PCI_SPEED_UNKNOWN;
|
|
|
|
- break;
|
|
|
|
- }
|
|
|
|
- } else {
|
|
|
|
- /* In the case where pi is undefined, default it to 1 */
|
|
|
|
- switch (sec_bus_status & 0x0007) {
|
|
|
|
- case 0:
|
|
|
|
- bus_speed = PCI_SPEED_33MHz;
|
|
|
|
- break;
|
|
|
|
- case 1:
|
|
|
|
- bus_speed = PCI_SPEED_66MHz;
|
|
|
|
- break;
|
|
|
|
- case 2:
|
|
|
|
- bus_speed = PCI_SPEED_66MHz_PCIX;
|
|
|
|
- break;
|
|
|
|
- case 3:
|
|
|
|
- bus_speed = PCI_SPEED_100MHz_PCIX;
|
|
|
|
- break;
|
|
|
|
- case 4:
|
|
|
|
- bus_speed = PCI_SPEED_133MHz_PCIX;
|
|
|
|
- break;
|
|
|
|
- case 5:
|
|
|
|
- bus_speed = PCI_SPEED_UNKNOWN; /* Reserved */
|
|
|
|
- break;
|
|
|
|
- case 6:
|
|
|
|
- bus_speed = PCI_SPEED_UNKNOWN; /* Reserved */
|
|
|
|
- break;
|
|
|
|
- case 7:
|
|
|
|
- bus_speed = PCI_SPEED_UNKNOWN; /* Reserved */
|
|
|
|
- break;
|
|
|
|
- default:
|
|
|
|
- bus_speed = PCI_SPEED_UNKNOWN;
|
|
|
|
- break;
|
|
|
|
- }
|
|
|
|
|
|
+ switch (speed_mode) {
|
|
|
|
+ case 0x0:
|
|
|
|
+ *value = PCI_SPEED_33MHz;
|
|
|
|
+ break;
|
|
|
|
+ case 0x1:
|
|
|
|
+ *value = PCI_SPEED_66MHz;
|
|
|
|
+ break;
|
|
|
|
+ case 0x2:
|
|
|
|
+ *value = PCI_SPEED_66MHz_PCIX;
|
|
|
|
+ break;
|
|
|
|
+ case 0x3:
|
|
|
|
+ *value = PCI_SPEED_100MHz_PCIX;
|
|
|
|
+ break;
|
|
|
|
+ case 0x4:
|
|
|
|
+ *value = PCI_SPEED_133MHz_PCIX;
|
|
|
|
+ break;
|
|
|
|
+ case 0x5:
|
|
|
|
+ *value = PCI_SPEED_66MHz_PCIX_ECC;
|
|
|
|
+ break;
|
|
|
|
+ case 0x6:
|
|
|
|
+ *value = PCI_SPEED_100MHz_PCIX_ECC;
|
|
|
|
+ break;
|
|
|
|
+ case 0x7:
|
|
|
|
+ *value = PCI_SPEED_133MHz_PCIX_ECC;
|
|
|
|
+ break;
|
|
|
|
+ case 0x8:
|
|
|
|
+ *value = PCI_SPEED_66MHz_PCIX_266;
|
|
|
|
+ break;
|
|
|
|
+ case 0x9:
|
|
|
|
+ *value = PCI_SPEED_100MHz_PCIX_266;
|
|
|
|
+ break;
|
|
|
|
+ case 0xa:
|
|
|
|
+ *value = PCI_SPEED_133MHz_PCIX_266;
|
|
|
|
+ break;
|
|
|
|
+ case 0xb:
|
|
|
|
+ *value = PCI_SPEED_66MHz_PCIX_533;
|
|
|
|
+ break;
|
|
|
|
+ case 0xc:
|
|
|
|
+ *value = PCI_SPEED_100MHz_PCIX_533;
|
|
|
|
+ break;
|
|
|
|
+ case 0xd:
|
|
|
|
+ *value = PCI_SPEED_133MHz_PCIX_533;
|
|
|
|
+ break;
|
|
|
|
+ default:
|
|
|
|
+ *value = PCI_SPEED_UNKNOWN;
|
|
|
|
+ retval = -ENODEV;
|
|
|
|
+ break;
|
|
}
|
|
}
|
|
|
|
|
|
- *value = bus_speed;
|
|
|
|
dbg("Current bus speed = %d\n", bus_speed);
|
|
dbg("Current bus speed = %d\n", bus_speed);
|
|
DBG_LEAVE_ROUTINE
|
|
DBG_LEAVE_ROUTINE
|
|
return retval;
|
|
return retval;
|