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@@ -25,6 +25,10 @@
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#define INTC_SYSSTATUS 0x0014
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#define INTC_SIR 0x0040
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#define INTC_CONTROL 0x0048
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+#define INTC_PROTECTION 0x004C
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+#define INTC_IDLE 0x0050
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+#define INTC_THRESHOLD 0x0068
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+#define INTC_MIR0 0x0084
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#define INTC_MIR_CLEAR0 0x0088
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#define INTC_MIR_SET0 0x008c
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#define INTC_PENDING_IRQ0 0x0098
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@@ -48,6 +52,18 @@ static struct omap_irq_bank {
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},
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};
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+/* Structure to save interrupt controller context */
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+struct omap3_intc_regs {
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+ u32 sysconfig;
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+ u32 protection;
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+ u32 idle;
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+ u32 threshold;
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+ u32 ilr[INTCPS_NR_IRQS];
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+ u32 mir[INTCPS_NR_MIR_REGS];
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+};
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+
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+static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
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+
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/* INTC bank register get/set */
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static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
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@@ -209,3 +225,53 @@ void __init omap_init_irq(void)
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}
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}
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+#ifdef CONFIG_ARCH_OMAP3
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+void omap_intc_save_context(void)
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+{
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+ int ind = 0, i = 0;
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+ for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
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+ struct omap_irq_bank *bank = irq_banks + ind;
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+ intc_context[ind].sysconfig =
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+ intc_bank_read_reg(bank, INTC_SYSCONFIG);
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+ intc_context[ind].protection =
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+ intc_bank_read_reg(bank, INTC_PROTECTION);
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+ intc_context[ind].idle =
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+ intc_bank_read_reg(bank, INTC_IDLE);
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+ intc_context[ind].threshold =
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+ intc_bank_read_reg(bank, INTC_THRESHOLD);
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+ for (i = 0; i < INTCPS_NR_IRQS; i++)
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+ intc_context[ind].ilr[i] =
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+ intc_bank_read_reg(bank, (0x100 + 0x4*ind));
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+ for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
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+ intc_context[ind].mir[i] =
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+ intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
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+ (0x20 * i));
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+ }
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+}
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+
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+void omap_intc_restore_context(void)
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+{
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+ int ind = 0, i = 0;
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+
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+ for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
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+ struct omap_irq_bank *bank = irq_banks + ind;
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+ intc_bank_write_reg(intc_context[ind].sysconfig,
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+ bank, INTC_SYSCONFIG);
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+ intc_bank_write_reg(intc_context[ind].sysconfig,
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+ bank, INTC_SYSCONFIG);
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+ intc_bank_write_reg(intc_context[ind].protection,
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+ bank, INTC_PROTECTION);
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+ intc_bank_write_reg(intc_context[ind].idle,
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+ bank, INTC_IDLE);
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+ intc_bank_write_reg(intc_context[ind].threshold,
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+ bank, INTC_THRESHOLD);
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+ for (i = 0; i < INTCPS_NR_IRQS; i++)
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+ intc_bank_write_reg(intc_context[ind].ilr[i],
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+ bank, (0x100 + 0x4*ind));
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+ for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
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+ intc_bank_write_reg(intc_context[ind].mir[i],
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+ &irq_banks[0], INTC_MIR0 + (0x20 * i));
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+ }
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+ /* MIRs are saved and restore with other PRCM registers */
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+}
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+#endif /* CONFIG_ARCH_OMAP3 */
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