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@@ -162,13 +162,76 @@ int samsung_usbphy_set_type(struct usb_phy *phy,
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}
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EXPORT_SYMBOL_GPL(samsung_usbphy_set_type);
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+int samsung_usbphy_rate_to_clksel_64xx(struct samsung_usbphy *sphy,
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+ unsigned long rate)
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+{
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+ unsigned int clksel;
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+
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+ switch (rate) {
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+ case 12 * MHZ:
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+ clksel = PHYCLK_CLKSEL_12M;
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+ break;
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+ case 24 * MHZ:
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+ clksel = PHYCLK_CLKSEL_24M;
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+ break;
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+ case 48 * MHZ:
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+ clksel = PHYCLK_CLKSEL_48M;
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+ break;
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+ default:
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+ dev_err(sphy->dev,
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+ "Invalid reference clock frequency: %lu\n", rate);
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+ return -EINVAL;
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+ }
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+
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+ return clksel;
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+}
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+EXPORT_SYMBOL_GPL(samsung_usbphy_rate_to_clksel_64xx);
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+
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+int samsung_usbphy_rate_to_clksel_4x12(struct samsung_usbphy *sphy,
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+ unsigned long rate)
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+{
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+ unsigned int clksel;
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+
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+ switch (rate) {
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+ case 9600 * KHZ:
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+ clksel = FSEL_CLKSEL_9600K;
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+ break;
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+ case 10 * MHZ:
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+ clksel = FSEL_CLKSEL_10M;
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+ break;
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+ case 12 * MHZ:
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+ clksel = FSEL_CLKSEL_12M;
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+ break;
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+ case 19200 * KHZ:
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+ clksel = FSEL_CLKSEL_19200K;
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+ break;
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+ case 20 * MHZ:
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+ clksel = FSEL_CLKSEL_20M;
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+ break;
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+ case 24 * MHZ:
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+ clksel = FSEL_CLKSEL_24M;
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+ break;
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+ case 50 * MHZ:
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+ clksel = FSEL_CLKSEL_50M;
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+ break;
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+ default:
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+ dev_err(sphy->dev,
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+ "Invalid reference clock frequency: %lu\n", rate);
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+ return -EINVAL;
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+ }
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+
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+ return clksel;
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+}
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+EXPORT_SYMBOL_GPL(samsung_usbphy_rate_to_clksel_4x12);
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+
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/*
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* Returns reference clock frequency selection value
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*/
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int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
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{
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struct clk *ref_clk;
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- int refclk_freq = 0;
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+ unsigned long rate;
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+ int refclk_freq;
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/*
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* In exynos5250 USB host and device PHY use
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@@ -183,52 +246,9 @@ int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
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return PTR_ERR(ref_clk);
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}
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- if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250) {
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- /* set clock frequency for PLL */
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- switch (clk_get_rate(ref_clk)) {
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- case 9600 * KHZ:
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- refclk_freq = FSEL_CLKSEL_9600K;
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- break;
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- case 10 * MHZ:
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- refclk_freq = FSEL_CLKSEL_10M;
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- break;
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- case 12 * MHZ:
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- refclk_freq = FSEL_CLKSEL_12M;
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- break;
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- case 19200 * KHZ:
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- refclk_freq = FSEL_CLKSEL_19200K;
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- break;
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- case 20 * MHZ:
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- refclk_freq = FSEL_CLKSEL_20M;
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- break;
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- case 50 * MHZ:
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- refclk_freq = FSEL_CLKSEL_50M;
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- break;
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- case 24 * MHZ:
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- default:
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- /* default reference clock */
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- refclk_freq = FSEL_CLKSEL_24M;
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- break;
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- }
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- } else {
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- switch (clk_get_rate(ref_clk)) {
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- case 12 * MHZ:
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- refclk_freq = PHYCLK_CLKSEL_12M;
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- break;
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- case 24 * MHZ:
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- refclk_freq = PHYCLK_CLKSEL_24M;
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- break;
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- case 48 * MHZ:
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- refclk_freq = PHYCLK_CLKSEL_48M;
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- break;
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- default:
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- if (sphy->drv_data->cpu_type == TYPE_S3C64XX)
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- refclk_freq = PHYCLK_CLKSEL_48M;
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- else
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- refclk_freq = PHYCLK_CLKSEL_24M;
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- break;
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- }
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- }
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+ rate = clk_get_rate(ref_clk);
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+ refclk_freq = sphy->drv_data->rate_to_clksel(sphy, rate);
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+
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clk_put(ref_clk);
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return refclk_freq;
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