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@@ -68,8 +68,7 @@ ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex,
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* the channel value. Assumes writes enabled to analog bus and bank6 register
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* cache in ah->analogBank6Data.
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*/
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-bool
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-ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
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+int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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u32 channelSel = 0;
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@@ -94,7 +93,7 @@ ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
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} else {
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ath_print(common, ATH_DBG_FATAL,
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"Invalid channel %u MHz\n", freq);
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- return false;
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+ return -EINVAL;
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}
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channelSel = (channelSel << 2) & 0xff;
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@@ -127,7 +126,7 @@ ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
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} else {
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ath_print(common, ATH_DBG_FATAL,
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"Invalid channel %u MHz\n", freq);
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- return false;
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+ return -EINVAL;
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}
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reg32 =
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@@ -139,7 +138,7 @@ ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
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ah->curchan = chan;
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ah->curchan_rad_index = -1;
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- return true;
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+ return 0;
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}
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/**
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@@ -163,8 +162,7 @@ ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
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* Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
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* (freq_ref = 40MHz/(24>>amodeRefSel))
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*/
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-void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
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- struct ath9k_channel *chan)
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+int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
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{
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u16 bMode, fracMode, aModeRefSel = 0;
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u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
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@@ -252,6 +250,8 @@ void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
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ah->curchan = chan;
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ah->curchan_rad_index = -1;
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+
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+ return 0;
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}
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/**
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