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@@ -89,7 +89,9 @@
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#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
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#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500)
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+#define S5P_CLKDIV_CPU1 S5P_CLKREG(0x14504)
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#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600)
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+#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604)
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#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
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@@ -100,6 +102,7 @@
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#define S5P_APLLCON0_ENABLE_SHIFT (31)
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#define S5P_APLLCON0_LOCKED_SHIFT (29)
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#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
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+#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
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/* CLK_SRC_CPU */
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#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
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