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@@ -366,6 +366,75 @@ bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
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return true;
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}
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+void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
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+{
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+ struct rtl_priv *rtlpriv = rtl_priv(hw);
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+ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
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+ struct rtl_phy *rtlphy = &(rtlpriv->phy);
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+ struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
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+ u8 reg_bw_opmode;
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+ u8 reg_prsr_rsc;
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+
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+ RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
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+ ("Switch to %s bandwidth\n",
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+ rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
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+ "20MHz" : "40MHz"))
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+
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+ if (is_hal_stop(rtlhal)) {
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+ rtlphy->set_bwmode_inprogress = false;
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+ return;
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+ }
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+
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+ reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
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+ reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
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+
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+ switch (rtlphy->current_chan_bw) {
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+ case HT_CHANNEL_WIDTH_20:
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+ reg_bw_opmode |= BW_OPMODE_20MHZ;
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+ rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
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+ break;
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+ case HT_CHANNEL_WIDTH_20_40:
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+ reg_bw_opmode &= ~BW_OPMODE_20MHZ;
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+ rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
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+ reg_prsr_rsc =
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+ (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
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+ rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
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+ break;
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+ default:
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+ RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
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+ ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
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+ break;
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+ }
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+
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+ switch (rtlphy->current_chan_bw) {
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+ case HT_CHANNEL_WIDTH_20:
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+ rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
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+ rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
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+ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
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+ break;
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+ case HT_CHANNEL_WIDTH_20_40:
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+ rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
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+ rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
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+
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+ rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
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+ (mac->cur_40_prime_sc >> 1));
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+ rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
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+ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
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+
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+ rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
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+ (mac->cur_40_prime_sc ==
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+ HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
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+ break;
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+ default:
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+ RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
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+ ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
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+ break;
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+ }
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+ rtl92ce_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
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+ rtlphy->set_bwmode_inprogress = false;
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+ RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
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+}
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+
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void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
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{
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u8 tmpreg;
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