|
@@ -163,7 +163,7 @@ static DEFINE_PER_CPU(u64, current_tsc_ratio);
|
|
|
|
|
|
#define MSR_INVALID 0xffffffffU
|
|
|
|
|
|
-static struct svm_direct_access_msrs {
|
|
|
+static const struct svm_direct_access_msrs {
|
|
|
u32 index; /* Index of the MSR */
|
|
|
bool always; /* True if intercept is always on */
|
|
|
} direct_access_msrs[] = {
|
|
@@ -400,7 +400,7 @@ struct svm_init_data {
|
|
|
int r;
|
|
|
};
|
|
|
|
|
|
-static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
|
|
|
+static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
|
|
|
|
|
|
#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
|
|
|
#define MSRS_RANGE_SIZE 2048
|
|
@@ -3267,7 +3267,7 @@ static int pause_interception(struct vcpu_svm *svm)
|
|
|
return 1;
|
|
|
}
|
|
|
|
|
|
-static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
|
|
|
+static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
|
|
|
[SVM_EXIT_READ_CR0] = cr_interception,
|
|
|
[SVM_EXIT_READ_CR3] = cr_interception,
|
|
|
[SVM_EXIT_READ_CR4] = cr_interception,
|
|
@@ -4068,7 +4068,7 @@ static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
|
|
|
#define POST_MEM(exit) { .exit_code = (exit), \
|
|
|
.stage = X86_ICPT_POST_MEMACCESS, }
|
|
|
|
|
|
-static struct __x86_intercept {
|
|
|
+static const struct __x86_intercept {
|
|
|
u32 exit_code;
|
|
|
enum x86_intercept_stage stage;
|
|
|
} x86_intercept_map[] = {
|