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@@ -491,13 +491,11 @@ static void domain_update_iommu_coherency(struct dmar_domain *domain)
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domain->iommu_coherency = 1;
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- i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
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- for (; i < g_num_of_iommus; ) {
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+ for_each_set_bit(i, &domain->iommu_bmp, g_num_of_iommus) {
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if (!ecap_coherent(g_iommus[i]->ecap)) {
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domain->iommu_coherency = 0;
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break;
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}
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- i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
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}
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}
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@@ -507,13 +505,11 @@ static void domain_update_iommu_snooping(struct dmar_domain *domain)
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domain->iommu_snooping = 1;
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- i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
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- for (; i < g_num_of_iommus; ) {
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+ for_each_set_bit(i, &domain->iommu_bmp, g_num_of_iommus) {
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if (!ecap_sc_support(g_iommus[i]->ecap)) {
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domain->iommu_snooping = 0;
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break;
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}
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- i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
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}
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}
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@@ -1068,7 +1064,7 @@ static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
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}
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static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
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- unsigned long pfn, unsigned int pages)
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+ unsigned long pfn, unsigned int pages, int map)
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{
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unsigned int mask = ilog2(__roundup_pow_of_two(pages));
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uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
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@@ -1089,10 +1085,10 @@ static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
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DMA_TLB_PSI_FLUSH);
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/*
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- * In caching mode, domain ID 0 is reserved for non-present to present
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- * mapping flush. Device IOTLB doesn't need to be flushed in this case.
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+ * In caching mode, changes of pages from non-present to present require
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+ * flush. However, device IOTLB doesn't need to be flushed in this case.
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*/
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- if (!cap_caching_mode(iommu->cap) || did)
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+ if (!cap_caching_mode(iommu->cap) || !map)
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iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
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}
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@@ -1154,7 +1150,8 @@ static int iommu_init_domains(struct intel_iommu *iommu)
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unsigned long nlongs;
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ndomains = cap_ndoms(iommu->cap);
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- pr_debug("Number of Domains supportd <%ld>\n", ndomains);
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+ pr_debug("IOMMU %d: Number of Domains supportd <%ld>\n", iommu->seq_id,
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+ ndomains);
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nlongs = BITS_TO_LONGS(ndomains);
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spin_lock_init(&iommu->lock);
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@@ -1194,8 +1191,7 @@ void free_dmar_iommu(struct intel_iommu *iommu)
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unsigned long flags;
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if ((iommu->domains) && (iommu->domain_ids)) {
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- i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
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- for (; i < cap_ndoms(iommu->cap); ) {
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+ for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) {
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domain = iommu->domains[i];
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clear_bit(i, iommu->domain_ids);
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@@ -1207,9 +1203,6 @@ void free_dmar_iommu(struct intel_iommu *iommu)
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domain_exit(domain);
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}
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spin_unlock_irqrestore(&domain->iommu_lock, flags);
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-
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- i = find_next_bit(iommu->domain_ids,
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- cap_ndoms(iommu->cap), i+1);
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}
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}
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@@ -1292,14 +1285,11 @@ static void iommu_detach_domain(struct dmar_domain *domain,
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spin_lock_irqsave(&iommu->lock, flags);
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ndomains = cap_ndoms(iommu->cap);
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- num = find_first_bit(iommu->domain_ids, ndomains);
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- for (; num < ndomains; ) {
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+ for_each_set_bit(num, iommu->domain_ids, ndomains) {
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if (iommu->domains[num] == domain) {
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found = 1;
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break;
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}
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- num = find_next_bit(iommu->domain_ids,
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- cap_ndoms(iommu->cap), num+1);
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}
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if (found) {
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@@ -1485,15 +1475,12 @@ static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
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/* find an available domain id for this device in iommu */
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ndomains = cap_ndoms(iommu->cap);
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- num = find_first_bit(iommu->domain_ids, ndomains);
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- for (; num < ndomains; ) {
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+ for_each_set_bit(num, iommu->domain_ids, ndomains) {
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if (iommu->domains[num] == domain) {
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id = num;
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found = 1;
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break;
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}
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- num = find_next_bit(iommu->domain_ids,
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- cap_ndoms(iommu->cap), num+1);
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}
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if (found == 0) {
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@@ -1558,7 +1545,7 @@ static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
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(((u16)bus) << 8) | devfn,
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DMA_CCMD_MASK_NOBIT,
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DMA_CCMD_DEVICE_INVL);
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- iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
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+ iommu->flush.flush_iotlb(iommu, domain->id, 0, 0, DMA_TLB_DSI_FLUSH);
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} else {
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iommu_flush_write_buffer(iommu);
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}
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@@ -2333,14 +2320,16 @@ int __init init_dmars(void)
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*/
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iommu->flush.flush_context = __iommu_flush_context;
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iommu->flush.flush_iotlb = __iommu_flush_iotlb;
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- printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
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+ printk(KERN_INFO "IOMMU %d 0x%Lx: using Register based "
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"invalidation\n",
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+ iommu->seq_id,
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(unsigned long long)drhd->reg_base_addr);
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} else {
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iommu->flush.flush_context = qi_flush_context;
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iommu->flush.flush_iotlb = qi_flush_iotlb;
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- printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
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+ printk(KERN_INFO "IOMMU %d 0x%Lx: using Queued "
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"invalidation\n",
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+ iommu->seq_id,
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(unsigned long long)drhd->reg_base_addr);
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}
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}
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@@ -2621,7 +2610,7 @@ static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
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/* it's a non-present to present mapping. Only flush if caching mode */
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if (cap_caching_mode(iommu->cap))
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- iommu_flush_iotlb_psi(iommu, 0, mm_to_dma_pfn(iova->pfn_lo), size);
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+ iommu_flush_iotlb_psi(iommu, domain->id, mm_to_dma_pfn(iova->pfn_lo), size, 1);
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else
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iommu_flush_write_buffer(iommu);
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@@ -2661,15 +2650,24 @@ static void flush_unmaps(void)
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if (!deferred_flush[i].next)
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continue;
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- iommu->flush.flush_iotlb(iommu, 0, 0, 0,
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+ /* In caching mode, global flushes turn emulation expensive */
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+ if (!cap_caching_mode(iommu->cap))
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+ iommu->flush.flush_iotlb(iommu, 0, 0, 0,
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DMA_TLB_GLOBAL_FLUSH);
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for (j = 0; j < deferred_flush[i].next; j++) {
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unsigned long mask;
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struct iova *iova = deferred_flush[i].iova[j];
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-
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- mask = ilog2(mm_to_dma_pfn(iova->pfn_hi - iova->pfn_lo + 1));
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- iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
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- (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
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+ struct dmar_domain *domain = deferred_flush[i].domain[j];
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+
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+ /* On real hardware multiple invalidations are expensive */
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+ if (cap_caching_mode(iommu->cap))
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+ iommu_flush_iotlb_psi(iommu, domain->id,
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+ iova->pfn_lo, iova->pfn_hi - iova->pfn_lo + 1, 0);
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+ else {
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+ mask = ilog2(mm_to_dma_pfn(iova->pfn_hi - iova->pfn_lo + 1));
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+ iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
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+ (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
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+ }
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__free_iova(&deferred_flush[i].domain[j]->iovad, iova);
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}
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deferred_flush[i].next = 0;
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@@ -2750,7 +2748,7 @@ static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
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if (intel_iommu_strict) {
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iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
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- last_pfn - start_pfn + 1);
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+ last_pfn - start_pfn + 1, 0);
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/* free iova */
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__free_iova(&domain->iovad, iova);
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} else {
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@@ -2840,7 +2838,7 @@ static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
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if (intel_iommu_strict) {
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iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
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- last_pfn - start_pfn + 1);
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+ last_pfn - start_pfn + 1, 0);
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/* free iova */
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__free_iova(&domain->iovad, iova);
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} else {
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@@ -2874,7 +2872,6 @@ static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int ne
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struct dmar_domain *domain;
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size_t size = 0;
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int prot = 0;
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- size_t offset_pfn = 0;
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struct iova *iova = NULL;
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int ret;
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struct scatterlist *sg;
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@@ -2928,7 +2925,7 @@ static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int ne
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/* it's a non-present to present mapping. Only flush if caching mode */
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if (cap_caching_mode(iommu->cap))
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- iommu_flush_iotlb_psi(iommu, 0, start_vpfn, offset_pfn);
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+ iommu_flush_iotlb_psi(iommu, domain->id, start_vpfn, size, 1);
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else
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iommu_flush_write_buffer(iommu);
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@@ -3436,22 +3433,6 @@ static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
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/* domain id for virtual machine, it won't be set in context */
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static unsigned long vm_domid;
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-static int vm_domain_min_agaw(struct dmar_domain *domain)
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-{
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- int i;
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- int min_agaw = domain->agaw;
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-
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- i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
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- for (; i < g_num_of_iommus; ) {
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- if (min_agaw > g_iommus[i]->agaw)
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- min_agaw = g_iommus[i]->agaw;
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-
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- i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
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- }
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-
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- return min_agaw;
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-}
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-
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static struct dmar_domain *iommu_alloc_vm_domain(void)
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{
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struct dmar_domain *domain;
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@@ -3512,8 +3493,7 @@ static void iommu_free_vm_domain(struct dmar_domain *domain)
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iommu = drhd->iommu;
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ndomains = cap_ndoms(iommu->cap);
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- i = find_first_bit(iommu->domain_ids, ndomains);
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- for (; i < ndomains; ) {
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+ for_each_set_bit(i, iommu->domain_ids, ndomains) {
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if (iommu->domains[i] == domain) {
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spin_lock_irqsave(&iommu->lock, flags);
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clear_bit(i, iommu->domain_ids);
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@@ -3521,7 +3501,6 @@ static void iommu_free_vm_domain(struct dmar_domain *domain)
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spin_unlock_irqrestore(&iommu->lock, flags);
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break;
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}
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- i = find_next_bit(iommu->domain_ids, ndomains, i+1);
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}
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}
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}
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@@ -3582,7 +3561,6 @@ static int intel_iommu_attach_device(struct iommu_domain *domain,
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struct pci_dev *pdev = to_pci_dev(dev);
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struct intel_iommu *iommu;
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int addr_width;
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- u64 end;
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/* normally pdev is not mapped */
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if (unlikely(domain_context_mapped(pdev))) {
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@@ -3605,14 +3583,30 @@ static int intel_iommu_attach_device(struct iommu_domain *domain,
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/* check if this iommu agaw is sufficient for max mapped address */
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addr_width = agaw_to_width(iommu->agaw);
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- end = DOMAIN_MAX_ADDR(addr_width);
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- end = end & VTD_PAGE_MASK;
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- if (end < dmar_domain->max_addr) {
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- printk(KERN_ERR "%s: iommu agaw (%d) is not "
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+ if (addr_width > cap_mgaw(iommu->cap))
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+ addr_width = cap_mgaw(iommu->cap);
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+
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+ if (dmar_domain->max_addr > (1LL << addr_width)) {
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+ printk(KERN_ERR "%s: iommu width (%d) is not "
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"sufficient for the mapped address (%llx)\n",
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- __func__, iommu->agaw, dmar_domain->max_addr);
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+ __func__, addr_width, dmar_domain->max_addr);
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return -EFAULT;
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}
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+ dmar_domain->gaw = addr_width;
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+
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+ /*
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+ * Knock out extra levels of page tables if necessary
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+ */
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+ while (iommu->agaw < dmar_domain->agaw) {
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+ struct dma_pte *pte;
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+
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+ pte = dmar_domain->pgd;
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+ if (dma_pte_present(pte)) {
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+ free_pgtable_page(dmar_domain->pgd);
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+ dmar_domain->pgd = (struct dma_pte *)dma_pte_addr(pte);
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+ }
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+ dmar_domain->agaw--;
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+ }
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return domain_add_dev_info(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
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}
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@@ -3632,7 +3626,6 @@ static int intel_iommu_map(struct iommu_domain *domain,
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{
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struct dmar_domain *dmar_domain = domain->priv;
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u64 max_addr;
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- int addr_width;
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int prot = 0;
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size_t size;
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int ret;
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@@ -3647,18 +3640,14 @@ static int intel_iommu_map(struct iommu_domain *domain,
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size = PAGE_SIZE << gfp_order;
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max_addr = iova + size;
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if (dmar_domain->max_addr < max_addr) {
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- int min_agaw;
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u64 end;
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/* check if minimum agaw is sufficient for mapped address */
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- min_agaw = vm_domain_min_agaw(dmar_domain);
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- addr_width = agaw_to_width(min_agaw);
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- end = DOMAIN_MAX_ADDR(addr_width);
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- end = end & VTD_PAGE_MASK;
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+ end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1;
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if (end < max_addr) {
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- printk(KERN_ERR "%s: iommu agaw (%d) is not "
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+ printk(KERN_ERR "%s: iommu width (%d) is not "
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"sufficient for the mapped address (%llx)\n",
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- __func__, min_agaw, max_addr);
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+ __func__, dmar_domain->gaw, max_addr);
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return -EFAULT;
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}
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dmar_domain->max_addr = max_addr;
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