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@@ -28,36 +28,6 @@
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static int forceload;
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module_param(forceload, bool, 0);
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-#define PCI_CFG_SPACE_SIZE (0x100)
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-int pci_find_aer_capability(struct pci_dev *dev)
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-{
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- int pos;
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- u32 reg32 = 0;
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-
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- /* Check if it's a pci-express device */
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- pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
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- if (!pos)
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- return 0;
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-
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- /* Check if it supports pci-express AER */
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- pos = PCI_CFG_SPACE_SIZE;
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- while (pos) {
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- if (pci_read_config_dword(dev, pos, ®32))
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- return 0;
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-
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- /* some broken boards return ~0 */
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- if (reg32 == 0xffffffff)
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- return 0;
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-
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- if (PCI_EXT_CAP_ID(reg32) == PCI_EXT_CAP_ID_ERR)
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- break;
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-
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- pos = reg32 >> 20;
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- }
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-
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- return pos;
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-}
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-
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int pci_enable_pcie_error_reporting(struct pci_dev *dev)
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{
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u16 reg16 = 0;
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@@ -67,6 +37,10 @@ int pci_enable_pcie_error_reporting(struct pci_dev *dev)
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if (!pos)
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return -EIO;
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+ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
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+ if (!pos)
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+ return -EIO;
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+
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pci_read_config_word(dev, pos+PCI_EXP_DEVCTL, ®16);
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reg16 = reg16 |
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PCI_EXP_DEVCTL_CERE |
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@@ -102,7 +76,7 @@ int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev)
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int pos;
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u32 status, mask;
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- pos = pci_find_aer_capability(dev);
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+ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
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if (!pos)
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return -EIO;
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@@ -123,7 +97,7 @@ int pci_cleanup_aer_correct_error_status(struct pci_dev *dev)
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int pos;
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u32 status;
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- pos = pci_find_aer_capability(dev);
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+ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
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if (!pos)
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return -EIO;
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@@ -502,7 +476,7 @@ static void handle_error_source(struct pcie_device * aerdev,
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* Correctable error does not need software intevention.
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* No need to go through error recovery process.
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*/
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- pos = pci_find_aer_capability(dev);
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+ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
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if (pos)
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pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS,
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info.status);
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@@ -542,7 +516,7 @@ void aer_enable_rootport(struct aer_rpc *rpc)
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reg16 &= ~(SYSTEM_ERROR_INTR_ON_MESG_MASK);
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pci_write_config_word(pdev, pos + PCI_EXP_RTCTL, reg16);
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- aer_pos = pci_find_aer_capability(pdev);
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+ aer_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
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/* Clear error status */
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pci_read_config_dword(pdev, aer_pos + PCI_ERR_ROOT_STATUS, ®32);
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pci_write_config_dword(pdev, aer_pos + PCI_ERR_ROOT_STATUS, reg32);
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@@ -579,7 +553,7 @@ static void disable_root_aer(struct aer_rpc *rpc)
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u32 reg32;
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int pos;
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- pos = pci_find_aer_capability(pdev);
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+ pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
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/* Disable Root's interrupt in response to error messages */
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pci_write_config_dword(pdev, pos + PCI_ERR_ROOT_COMMAND, 0);
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@@ -618,7 +592,7 @@ static int get_device_error_info(struct pci_dev *dev, struct aer_err_info *info)
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{
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int pos;
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- pos = pci_find_aer_capability(dev);
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+ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
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/* The device might not support AER */
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if (!pos)
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@@ -755,7 +729,6 @@ int aer_init(struct pcie_device *dev)
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return AER_SUCCESS;
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}
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-EXPORT_SYMBOL_GPL(pci_find_aer_capability);
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EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting);
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EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting);
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EXPORT_SYMBOL_GPL(pci_cleanup_aer_uncorrect_error_status);
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