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@@ -8654,7 +8654,7 @@ void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
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}
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/* Give HW time to discard old tx messages */
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- usleep_range(1000, 1000);
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+ usleep_range(1000, 2000);
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/* Clean all ETH MACs */
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rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
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@@ -9078,7 +9078,7 @@ static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
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if (pend_bits == 0)
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break;
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- usleep_range(1000, 1000);
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+ usleep_range(1000, 2000);
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} while (cnt-- > 0);
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if (cnt <= 0) {
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@@ -9113,7 +9113,7 @@ static int bnx2x_process_kill(struct bnx2x *bp, bool global)
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(pgl_exp_rom2 == 0xffffffff) &&
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(!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
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break;
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- usleep_range(1000, 1000);
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+ usleep_range(1000, 2000);
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} while (cnt-- > 0);
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if (cnt <= 0) {
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@@ -9146,7 +9146,7 @@ static int bnx2x_process_kill(struct bnx2x *bp, bool global)
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/* Wait for 1ms to empty GLUE and PCI-E core queues,
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* PSWHST, GRC and PSWRD Tetris buffer.
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*/
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- usleep_range(1000, 1000);
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+ usleep_range(1000, 2000);
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/* Prepare to chip reset: */
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/* MCP */
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@@ -10917,7 +10917,7 @@ static int bnx2x_get_hwinfo(struct bnx2x *bp)
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while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
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tout--;
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- usleep_range(1000, 1000);
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+ usleep_range(1000, 2000);
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}
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if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
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