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@@ -0,0 +1,449 @@
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+/*
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+ * SuperH Mobile SDHI
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+ *
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+ * Copyright (C) 2010 Magnus Damm
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+ * Copyright (C) 2010 Kuninori Morimoto
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+ * Copyright (C) 2010 Simon Horman
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+ *
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Parts inspired by u-boot
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+ */
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+
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+#include <linux/io.h>
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+#include <linux/mmc/host.h>
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+#include <linux/mmc/core.h>
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+#include <linux/mmc/mmc.h>
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+#include <linux/mmc/sd.h>
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+#include <linux/mmc/tmio.h>
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+#include <mach/sdhi.h>
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+
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+#define OCR_FASTBOOT (1<<29)
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+#define OCR_HCS (1<<30)
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+#define OCR_BUSY (1<<31)
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+
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+#define RESP_CMD12 0x00000030
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+
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+static inline u16 sd_ctrl_read16(void __iomem *base, int addr)
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+{
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+ return __raw_readw(base + addr);
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+}
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+
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+static inline u32 sd_ctrl_read32(void __iomem *base, int addr)
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+{
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+ return __raw_readw(base + addr) |
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+ __raw_readw(base + addr + 2) << 16;
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+}
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+
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+static inline void sd_ctrl_write16(void __iomem *base, int addr, u16 val)
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+{
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+ __raw_writew(val, base + addr);
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+}
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+
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+static inline void sd_ctrl_write32(void __iomem *base, int addr, u32 val)
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+{
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+ __raw_writew(val, base + addr);
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+ __raw_writew(val >> 16, base + addr + 2);
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+}
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+
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+#define ALL_ERROR (TMIO_STAT_CMD_IDX_ERR | TMIO_STAT_CRCFAIL | \
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+ TMIO_STAT_STOPBIT_ERR | TMIO_STAT_DATATIMEOUT | \
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+ TMIO_STAT_RXOVERFLOW | TMIO_STAT_TXUNDERRUN | \
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+ TMIO_STAT_CMDTIMEOUT | TMIO_STAT_ILL_ACCESS | \
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+ TMIO_STAT_ILL_FUNC)
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+
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+static int sdhi_intr(void __iomem *base)
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+{
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+ unsigned long state = sd_ctrl_read32(base, CTL_STATUS);
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+
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+ if (state & ALL_ERROR) {
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+ sd_ctrl_write32(base, CTL_STATUS, ~ALL_ERROR);
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+ sd_ctrl_write32(base, CTL_IRQ_MASK,
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+ ALL_ERROR |
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+ sd_ctrl_read32(base, CTL_IRQ_MASK));
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+ return -EINVAL;
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+ }
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+ if (state & TMIO_STAT_CMDRESPEND) {
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+ sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_CMDRESPEND);
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+ sd_ctrl_write32(base, CTL_IRQ_MASK,
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+ TMIO_STAT_CMDRESPEND |
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+ sd_ctrl_read32(base, CTL_IRQ_MASK));
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+ return 0;
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+ }
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+ if (state & TMIO_STAT_RXRDY) {
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+ sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_RXRDY);
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+ sd_ctrl_write32(base, CTL_IRQ_MASK,
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+ TMIO_STAT_RXRDY | TMIO_STAT_TXUNDERRUN |
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+ sd_ctrl_read32(base, CTL_IRQ_MASK));
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+ return 0;
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+ }
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+ if (state & TMIO_STAT_DATAEND) {
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+ sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_DATAEND);
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+ sd_ctrl_write32(base, CTL_IRQ_MASK,
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+ TMIO_STAT_DATAEND |
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+ sd_ctrl_read32(base, CTL_IRQ_MASK));
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+ return 0;
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+ }
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+
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+ return -EAGAIN;
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+}
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+
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+static int sdhi_boot_wait_resp_end(void __iomem *base)
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+{
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+ int err = -EAGAIN, timeout = 10000000;
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+
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+ while (timeout--) {
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+ err = sdhi_intr(base);
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+ if (err != -EAGAIN)
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+ break;
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+ udelay(1);
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+ }
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+
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+ return err;
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+}
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+
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+/* SDHI_CLK_CTRL */
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+#define CLK_MMC_ENABLE (1 << 8)
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+#define CLK_MMC_INIT (1 << 6) /* clk / 256 */
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+
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+static void sdhi_boot_mmc_clk_stop(void __iomem *base)
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+{
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+ sd_ctrl_write16(base, CTL_CLK_AND_WAIT_CTL, 0x0000);
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+ msleep(10);
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+ sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL, ~CLK_MMC_ENABLE &
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+ sd_ctrl_read16(base, CTL_SD_CARD_CLK_CTL));
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+ msleep(10);
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+}
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+
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+static void sdhi_boot_mmc_clk_start(void __iomem *base)
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+{
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+ sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL, CLK_MMC_ENABLE |
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+ sd_ctrl_read16(base, CTL_SD_CARD_CLK_CTL));
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+ msleep(10);
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+ sd_ctrl_write16(base, CTL_CLK_AND_WAIT_CTL, CLK_MMC_ENABLE);
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+ msleep(10);
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+}
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+
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+static void sdhi_boot_reset(void __iomem *base)
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+{
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+ sd_ctrl_write16(base, CTL_RESET_SD, 0x0000);
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+ msleep(10);
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+ sd_ctrl_write16(base, CTL_RESET_SD, 0x0001);
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+ msleep(10);
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+}
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+
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+/* Set MMC clock / power.
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+ * Note: This controller uses a simple divider scheme therefore it cannot
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+ * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
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+ * MMC wont run that fast, it has to be clocked at 12MHz which is the next
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+ * slowest setting.
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+ */
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+static int sdhi_boot_mmc_set_ios(void __iomem *base, struct mmc_ios *ios)
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+{
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+ if (sd_ctrl_read32(base, CTL_STATUS) & TMIO_STAT_CMD_BUSY)
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+ return -EBUSY;
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+
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+ if (ios->clock)
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+ sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL,
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+ ios->clock | CLK_MMC_ENABLE);
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+
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+ /* Power sequence - OFF -> ON -> UP */
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+ switch (ios->power_mode) {
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+ case MMC_POWER_OFF: /* power down SD bus */
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+ sdhi_boot_mmc_clk_stop(base);
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+ break;
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+ case MMC_POWER_ON: /* power up SD bus */
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+ break;
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+ case MMC_POWER_UP: /* start bus clock */
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+ sdhi_boot_mmc_clk_start(base);
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+ break;
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+ }
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+
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+ switch (ios->bus_width) {
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+ case MMC_BUS_WIDTH_1:
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+ sd_ctrl_write16(base, CTL_SD_MEM_CARD_OPT, 0x80e0);
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+ break;
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+ case MMC_BUS_WIDTH_4:
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+ sd_ctrl_write16(base, CTL_SD_MEM_CARD_OPT, 0x00e0);
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+ break;
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+ }
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+
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+ /* Let things settle. delay taken from winCE driver */
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+ udelay(140);
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+
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+ return 0;
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+}
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+
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+/* These are the bitmasks the tmio chip requires to implement the MMC response
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+ * types. Note that R1 and R6 are the same in this scheme. */
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+#define RESP_NONE 0x0300
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+#define RESP_R1 0x0400
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+#define RESP_R1B 0x0500
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+#define RESP_R2 0x0600
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+#define RESP_R3 0x0700
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+#define DATA_PRESENT 0x0800
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+#define TRANSFER_READ 0x1000
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+
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+static int sdhi_boot_request(void __iomem *base, struct mmc_command *cmd)
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+{
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+ int err, c = cmd->opcode;
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+
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+ switch (mmc_resp_type(cmd)) {
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+ case MMC_RSP_NONE: c |= RESP_NONE; break;
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+ case MMC_RSP_R1: c |= RESP_R1; break;
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+ case MMC_RSP_R1B: c |= RESP_R1B; break;
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+ case MMC_RSP_R2: c |= RESP_R2; break;
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+ case MMC_RSP_R3: c |= RESP_R3; break;
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+ default:
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+ return -EINVAL;
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+ }
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+
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+ /* No interrupts so this may not be cleared */
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+ sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_CMDRESPEND);
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+
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+ sd_ctrl_write32(base, CTL_IRQ_MASK, TMIO_STAT_CMDRESPEND |
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+ sd_ctrl_read32(base, CTL_IRQ_MASK));
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+ sd_ctrl_write32(base, CTL_ARG_REG, cmd->arg);
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+ sd_ctrl_write16(base, CTL_SD_CMD, c);
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+
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+
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+ sd_ctrl_write32(base, CTL_IRQ_MASK,
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+ ~(TMIO_STAT_CMDRESPEND | ALL_ERROR) &
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+ sd_ctrl_read32(base, CTL_IRQ_MASK));
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+
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+ err = sdhi_boot_wait_resp_end(base);
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+ if (err)
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+ return err;
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+
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+ cmd->resp[0] = sd_ctrl_read32(base, CTL_RESPONSE);
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+
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+ return 0;
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+}
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+
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+static int sdhi_boot_do_read_single(void __iomem *base, int high_capacity,
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+ unsigned long block, unsigned short *buf)
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+{
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+ int err, i;
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+
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+ /* CMD17 - Read */
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+ {
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+ struct mmc_command cmd;
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+
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+ cmd.opcode = MMC_READ_SINGLE_BLOCK | \
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+ TRANSFER_READ | DATA_PRESENT;
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+ if (high_capacity)
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+ cmd.arg = block;
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+ else
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+ cmd.arg = block * TMIO_BBS;
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+ cmd.flags = MMC_RSP_R1;
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+ err = sdhi_boot_request(base, &cmd);
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+ if (err)
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+ return err;
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+ }
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+
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+ sd_ctrl_write32(base, CTL_IRQ_MASK,
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+ ~(TMIO_STAT_DATAEND | TMIO_STAT_RXRDY |
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+ TMIO_STAT_TXUNDERRUN) &
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+ sd_ctrl_read32(base, CTL_IRQ_MASK));
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+ err = sdhi_boot_wait_resp_end(base);
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+ if (err)
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+ return err;
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+
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+ sd_ctrl_write16(base, CTL_SD_XFER_LEN, TMIO_BBS);
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+ for (i = 0; i < TMIO_BBS / sizeof(*buf); i++)
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+ *buf++ = sd_ctrl_read16(base, RESP_CMD12);
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+
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+ err = sdhi_boot_wait_resp_end(base);
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+ if (err)
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+ return err;
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+
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+ return 0;
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+}
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+
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+int sdhi_boot_do_read(void __iomem *base, int high_capacity,
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+ unsigned long offset, unsigned short count,
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+ unsigned short *buf)
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+{
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+ unsigned long i;
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+ int err = 0;
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+
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+ for (i = 0; i < count; i++) {
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+ err = sdhi_boot_do_read_single(base, high_capacity, offset + i,
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+ buf + (i * TMIO_BBS /
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+ sizeof(*buf)));
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+ if (err)
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+ return err;
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+ }
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+
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+ return 0;
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+}
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+
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+#define VOLTAGES (MMC_VDD_32_33 | MMC_VDD_33_34)
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+
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+int sdhi_boot_init(void __iomem *base)
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+{
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+ bool sd_v2 = false, sd_v1_0 = false;
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+ unsigned short cid;
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+ int err, high_capacity = 0;
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+
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+ sdhi_boot_mmc_clk_stop(base);
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+ sdhi_boot_reset(base);
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+
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+ /* mmc0: clock 400000Hz busmode 1 powermode 2 cs 0 Vdd 21 width 0 timing 0 */
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+ {
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+ struct mmc_ios ios;
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+ ios.power_mode = MMC_POWER_ON;
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+ ios.bus_width = MMC_BUS_WIDTH_1;
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+ ios.clock = CLK_MMC_INIT;
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+ err = sdhi_boot_mmc_set_ios(base, &ios);
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+ if (err)
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+ return err;
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+ }
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+
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+ /* CMD0 */
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+ {
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+ struct mmc_command cmd;
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+ msleep(1);
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+ cmd.opcode = MMC_GO_IDLE_STATE;
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+ cmd.arg = 0;
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+ cmd.flags = MMC_RSP_NONE;
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+ err = sdhi_boot_request(base, &cmd);
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+ if (err)
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+ return err;
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+ msleep(2);
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+ }
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+
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+ /* CMD8 - Test for SD version 2 */
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+ {
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+ struct mmc_command cmd;
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+ cmd.opcode = SD_SEND_IF_COND;
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+ cmd.arg = (VOLTAGES != 0) << 8 | 0xaa;
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+ cmd.flags = MMC_RSP_R1;
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+ err = sdhi_boot_request(base, &cmd); /* Ignore error */
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+ if ((cmd.resp[0] & 0xff) == 0xaa)
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+ sd_v2 = true;
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+ }
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+
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+ /* CMD55 - Get OCR (SD) */
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+ {
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+ int timeout = 1000;
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+ struct mmc_command cmd;
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+
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+ cmd.arg = 0;
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+
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+ do {
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+ cmd.opcode = MMC_APP_CMD;
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+ cmd.flags = MMC_RSP_R1;
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+ cmd.arg = 0;
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+ err = sdhi_boot_request(base, &cmd);
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+ if (err)
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+ break;
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+
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+ cmd.opcode = SD_APP_OP_COND;
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+ cmd.flags = MMC_RSP_R3;
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+ cmd.arg = (VOLTAGES & 0xff8000);
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+ if (sd_v2)
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+ cmd.arg |= OCR_HCS;
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+ cmd.arg |= OCR_FASTBOOT;
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+ err = sdhi_boot_request(base, &cmd);
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+ if (err)
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+ break;
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+
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+ msleep(1);
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+ } while((!(cmd.resp[0] & OCR_BUSY)) && --timeout);
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+
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+ if (!err && timeout) {
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+ if (!sd_v2)
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+ sd_v1_0 = true;
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+ high_capacity = (cmd.resp[0] & OCR_HCS) == OCR_HCS;
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+ }
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+ }
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+
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+ /* CMD1 - Get OCR (MMC) */
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+ if (!sd_v2 && !sd_v1_0) {
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+ int timeout = 1000;
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+ struct mmc_command cmd;
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+
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+ do {
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+ cmd.opcode = MMC_SEND_OP_COND;
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+ cmd.arg = VOLTAGES | OCR_HCS;
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+ cmd.flags = MMC_RSP_R3;
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+ err = sdhi_boot_request(base, &cmd);
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+ if (err)
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+ return err;
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+
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+ msleep(1);
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+ } while((!(cmd.resp[0] & OCR_BUSY)) && --timeout);
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+
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+ if (!timeout)
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+ return -EAGAIN;
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+
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+ high_capacity = (cmd.resp[0] & OCR_HCS) == OCR_HCS;
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+ }
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+
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+ /* CMD2 - Get CID */
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+ {
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+ struct mmc_command cmd;
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+ cmd.opcode = MMC_ALL_SEND_CID;
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+ cmd.arg = 0;
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+ cmd.flags = MMC_RSP_R2;
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+ err = sdhi_boot_request(base, &cmd);
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+ if (err)
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+ return err;
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+ }
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+
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+ /* CMD3
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+ * MMC: Set the relative address
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|
+ * SD: Get the relative address
|
|
|
+ * Also puts the card into the standby state
|
|
|
+ */
|
|
|
+ {
|
|
|
+ struct mmc_command cmd;
|
|
|
+ cmd.opcode = MMC_SET_RELATIVE_ADDR;
|
|
|
+ cmd.arg = 0;
|
|
|
+ cmd.flags = MMC_RSP_R1;
|
|
|
+ err = sdhi_boot_request(base, &cmd);
|
|
|
+ if (err)
|
|
|
+ return err;
|
|
|
+ cid = cmd.resp[0] >> 16;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* CMD9 - Get CSD */
|
|
|
+ {
|
|
|
+ struct mmc_command cmd;
|
|
|
+ cmd.opcode = MMC_SEND_CSD;
|
|
|
+ cmd.arg = cid << 16;
|
|
|
+ cmd.flags = MMC_RSP_R2;
|
|
|
+ err = sdhi_boot_request(base, &cmd);
|
|
|
+ if (err)
|
|
|
+ return err;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* CMD7 - Select the card */
|
|
|
+ {
|
|
|
+ struct mmc_command cmd;
|
|
|
+ cmd.opcode = MMC_SELECT_CARD;
|
|
|
+ //cmd.arg = rca << 16;
|
|
|
+ cmd.arg = cid << 16;
|
|
|
+ //cmd.flags = MMC_RSP_R1B;
|
|
|
+ cmd.flags = MMC_RSP_R1;
|
|
|
+ err = sdhi_boot_request(base, &cmd);
|
|
|
+ if (err)
|
|
|
+ return err;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* CMD16 - Set the block size */
|
|
|
+ {
|
|
|
+ struct mmc_command cmd;
|
|
|
+ cmd.opcode = MMC_SET_BLOCKLEN;
|
|
|
+ cmd.arg = TMIO_BBS;
|
|
|
+ cmd.flags = MMC_RSP_R1;
|
|
|
+ err = sdhi_boot_request(base, &cmd);
|
|
|
+ if (err)
|
|
|
+ return err;
|
|
|
+ }
|
|
|
+
|
|
|
+ return high_capacity;
|
|
|
+}
|
Simon Horman