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@@ -16,9 +16,7 @@
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* 2/3 chan to port 1, 4/5 chan to port 3. Even number chans
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* are used for RX, odd chans for TX
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*
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- * 2. In A0 stepping, UART will not support TX half empty flag
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- *
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- * 3. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
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+ * 2. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
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* asserted, only when the HW is reset the DDCD and DDSR will
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* be triggered
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*/
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@@ -41,8 +39,6 @@
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#include <linux/io.h>
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#include <linux/debugfs.h>
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-#define MFD_HSU_A0_STEPPING 1
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-
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#define HSU_DMA_BUF_SIZE 2048
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#define chan_readl(chan, offset) readl(chan->reg + offset)
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@@ -543,16 +539,9 @@ static void transmit_chars(struct uart_hsu_port *up)
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return;
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}
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-#ifndef MFD_HSU_A0_STEPPING
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+ /* The IRQ is for TX FIFO half-empty */
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count = up->port.fifosize / 2;
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-#else
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- /*
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- * A0 only supports fully empty IRQ, and the first char written
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- * into it won't clear the EMPT bit, so we may need be cautious
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- * by useing a shorter buffer
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- */
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- count = up->port.fifosize - 4;
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-#endif
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+
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do {
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serial_out(up, UART_TX, xmit->buf[xmit->tail]);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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@@ -761,9 +750,8 @@ static void serial_hsu_break_ctl(struct uart_port *port, int break_state)
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/*
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* What special to do:
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* 1. chose the 64B fifo mode
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- * 2. make sure not to select half empty mode for A0 stepping
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- * 3. start dma or pio depends on configuration
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- * 4. we only allocate dma memory when needed
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+ * 2. start dma or pio depends on configuration
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+ * 3. we only allocate dma memory when needed
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*/
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static int serial_hsu_startup(struct uart_port *port)
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{
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@@ -967,10 +955,6 @@ serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
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fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B;
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fcr |= UART_FCR_HSU_64B_FIFO;
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-#ifdef MFD_HSU_A0_STEPPING
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- /* A0 doesn't support half empty IRQ */
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- fcr |= UART_FCR_FULL_EMPT_TXI;
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-#endif
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/*
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* Ok, we're now changing the port state. Do it with
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