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@@ -135,7 +135,7 @@ typedef enum cy_as_hal_dma_type {
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cy_as_hal_read,
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cy_as_hal_write,
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cy_as_hal_none
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-} cy_as_hal_dma_type ;
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+} cy_as_hal_dma_type;
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/*
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@@ -146,9 +146,9 @@ typedef enum cy_as_hal_dma_type {
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((struct scatterlist *) ((sg)->page_link & ~0x03))
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*/
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typedef struct cy_as_hal_endpoint_dma {
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- cy_bool buffer_valid ;
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- uint8_t *data_p ;
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- uint32_t size ;
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+ cy_bool buffer_valid;
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+ uint8_t *data_p;
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+ uint32_t size;
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/*
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* sg_list_enabled - if true use, r/w DMA transfers use sg list,
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* FALSE use pointer to a buffer
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@@ -162,14 +162,14 @@ typedef struct cy_as_hal_endpoint_dma {
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* req_length - total request length
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*/
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bool sg_list_enabled;
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- struct scatterlist *sg_p ;
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+ struct scatterlist *sg_p;
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uint16_t dma_xfer_sz;
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uint32_t seg_xfer_cnt;
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uint16_t req_xfer_cnt;
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uint16_t req_length;
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- cy_as_hal_dma_type type ;
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- cy_bool pending ;
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-} cy_as_hal_endpoint_dma ;
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+ cy_as_hal_dma_type type;
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+ cy_bool pending;
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+} cy_as_hal_endpoint_dma;
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/*
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* The list of OMAP devices (should be one)
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@@ -184,7 +184,7 @@ static cy_as_hal_dma_complete_callback callback;
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/*
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* Pending data size for the endpoints
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*/
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-static cy_as_hal_endpoint_dma end_points[16] ;
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+static cy_as_hal_endpoint_dma end_points[16];
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/*
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* Forward declaration
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@@ -193,7 +193,7 @@ static void cy_handle_d_r_q_interrupt(cy_as_omap_dev_kernel *dev_p);
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static uint16_t intr_sequence_num;
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static uint8_t intr__enable;
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-spinlock_t int_lock ;
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+spinlock_t int_lock;
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static u32 iomux_vma;
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static u32 csa_phy;
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@@ -201,7 +201,7 @@ static u32 csa_phy;
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/*
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* gpmc I/O registers VMA
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*/
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-static u32 gpmc_base ;
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+static u32 gpmc_base;
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/*
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* gpmc data VMA associated with CS4 (ASTORIA CS on GPMC)
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@@ -496,8 +496,8 @@ static irqreturn_t cy_astoria_int_handler(int irq,
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void *dev_id, struct pt_regs *regs)
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{
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cy_as_omap_dev_kernel *dev_p;
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- uint16_t read_val = 0 ;
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- uint16_t mask_val = 0 ;
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+ uint16_t read_val = 0;
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+ uint16_t mask_val = 0;
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/*
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* debug stuff, counts number of loops per one intr trigger
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@@ -520,7 +520,7 @@ static irqreturn_t cy_astoria_int_handler(int irq,
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/*
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* this one just for debugging
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*/
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- intr_sequence_num++ ;
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+ intr_sequence_num++;
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/*
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* astoria device handle
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@@ -531,13 +531,13 @@ static irqreturn_t cy_astoria_int_handler(int irq,
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* read Astoria intr register
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*/
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read_val = cy_as_hal_read_register((cy_as_hal_device_tag)dev_p,
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- CY_AS_MEM_P0_INTR_REG) ;
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+ CY_AS_MEM_P0_INTR_REG);
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/*
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* save current mask value
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*/
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mask_val = cy_as_hal_read_register((cy_as_hal_device_tag)dev_p,
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- CY_AS_MEM_P0_INT_MASK_REG) ;
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+ CY_AS_MEM_P0_INT_MASK_REG);
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DBGPRN("<1>HAL__intr__enter:_seq:%d, P0_INTR_REG:%x\n",
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intr_sequence_num, read_val);
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@@ -546,7 +546,7 @@ static irqreturn_t cy_astoria_int_handler(int irq,
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* Disable WB interrupt signal generation while we are in ISR
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*/
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cy_as_hal_write_register((cy_as_hal_device_tag)dev_p,
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- CY_AS_MEM_P0_INT_MASK_REG, 0x0000) ;
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+ CY_AS_MEM_P0_INT_MASK_REG, 0x0000);
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/*
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* this is a DRQ Interrupt
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@@ -559,7 +559,7 @@ static irqreturn_t cy_astoria_int_handler(int irq,
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*/
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drq_loop_cnt++;
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- cy_handle_d_r_q_interrupt(dev_p) ;
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+ cy_handle_d_r_q_interrupt(dev_p);
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/*
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* spending to much time in ISR may impact
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@@ -577,7 +577,7 @@ static irqreturn_t cy_astoria_int_handler(int irq,
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}
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if (read_val & sentinel)
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- cy_as_intr_service_interrupt((cy_as_hal_device_tag)dev_p) ;
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+ cy_as_intr_service_interrupt((cy_as_hal_device_tag)dev_p);
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DBGPRN("<1>_hal:_intr__exit seq:%d, mask=%4.4x,"
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"int_pin:%d DRQ_jobs:%d\n",
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@@ -590,9 +590,9 @@ static irqreturn_t cy_astoria_int_handler(int irq,
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* re-enable WB hw interrupts
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*/
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cy_as_hal_write_register((cy_as_hal_device_tag)dev_p,
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- CY_AS_MEM_P0_INT_MASK_REG, mask_val) ;
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+ CY_AS_MEM_P0_INT_MASK_REG, mask_val);
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- return IRQ_HANDLED ;
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+ return IRQ_HANDLED;
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}
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static int cy_as_hal_configure_interrupts(void *dev_p)
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@@ -827,34 +827,34 @@ void cy_as_hal_omap_hardware_deinit(cy_as_omap_dev_kernel *dev_p)
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*/
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int stop_o_m_a_p_kernel(const char *pgm, cy_as_hal_device_tag tag)
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{
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- cy_as_omap_dev_kernel *dev_p = (cy_as_omap_dev_kernel *)tag ;
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+ cy_as_omap_dev_kernel *dev_p = (cy_as_omap_dev_kernel *)tag;
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/*
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* TODO: Need to disable WB interrupt handlere 1st
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*/
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if (0 == dev_p)
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- return 1 ;
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+ return 1;
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cy_as_hal_print_message("<1>_stopping OMAP34xx HAL layer object\n");
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if (dev_p->m_sig != CY_AS_OMAP_KERNEL_HAL_SIG) {
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cy_as_hal_print_message("<1>%s: %s: bad HAL tag\n",
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- pgm, __func__) ;
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- return 1 ;
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+ pgm, __func__);
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+ return 1;
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}
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/*
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* disable interrupt
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*/
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cy_as_hal_write_register((cy_as_hal_device_tag)dev_p,
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- CY_AS_MEM_P0_INT_MASK_REG, 0x0000) ;
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+ CY_AS_MEM_P0_INT_MASK_REG, 0x0000);
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#if 0
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if (dev_p->thread_flag == 0) {
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- dev_p->thread_flag = 1 ;
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- wait_for_completion(&dev_p->thread_complete) ;
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+ dev_p->thread_flag = 1;
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+ wait_for_completion(&dev_p->thread_complete);
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cy_as_hal_print_message("cyasomaphal:"
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"done cleaning thread\n");
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- cy_as_hal_destroy_sleep_channel(&dev_p->thread_sc) ;
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+ cy_as_hal_destroy_sleep_channel(&dev_p->thread_sc);
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}
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#endif
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@@ -864,9 +864,9 @@ int stop_o_m_a_p_kernel(const char *pgm, cy_as_hal_device_tag tag)
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* Rearrange the list
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*/
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if (m_omap_list_p == dev_p)
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- m_omap_list_p = dev_p->m_next_p ;
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+ m_omap_list_p = dev_p->m_next_p;
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- cy_as_hal_free(dev_p) ;
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+ cy_as_hal_free(dev_p);
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cy_as_hal_print_message(KERN_INFO"OMAP_kernel_hal stopped\n");
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return 0;
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@@ -874,23 +874,23 @@ int stop_o_m_a_p_kernel(const char *pgm, cy_as_hal_device_tag tag)
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int omap_start_intr(cy_as_hal_device_tag tag)
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{
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- cy_as_omap_dev_kernel *dev_p = (cy_as_omap_dev_kernel *)tag ;
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- int ret = 0 ;
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+ cy_as_omap_dev_kernel *dev_p = (cy_as_omap_dev_kernel *)tag;
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+ int ret = 0;
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const uint16_t mask = CY_AS_MEM_P0_INTR_REG_DRQINT |
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- CY_AS_MEM_P0_INTR_REG_MBINT ;
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+ CY_AS_MEM_P0_INTR_REG_MBINT;
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/*
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* register for interrupts
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*/
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- ret = cy_as_hal_configure_interrupts(dev_p) ;
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+ ret = cy_as_hal_configure_interrupts(dev_p);
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/*
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* enable only MBox & DRQ interrupts for now
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*/
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cy_as_hal_write_register((cy_as_hal_device_tag)dev_p,
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- CY_AS_MEM_P0_INT_MASK_REG, mask) ;
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+ CY_AS_MEM_P0_INT_MASK_REG, mask);
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- return 1 ;
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+ return 1;
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}
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/*
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@@ -1175,7 +1175,7 @@ static void p_nand_lbd_read(u16 col_addr, u32 row_addr, u16 count, void *buff)
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ptr32 = buff;
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do {
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- pfe_status = IORD32(GPMC_VMA(GPMC_PREFETCH_STATUS)) ;
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+ pfe_status = IORD32(GPMC_VMA(GPMC_PREFETCH_STATUS));
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rd_cnt = pfe_status >> (24+2);
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while (rd_cnt--)
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@@ -1481,14 +1481,14 @@ void cy_as_hal_write_register(
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*/
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uint16_t cy_as_hal_read_register(cy_as_hal_device_tag tag, uint16_t addr)
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{
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- uint16_t data = 0 ;
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+ uint16_t data = 0;
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/*
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* READ ASTORIA REGISTER USING CASDO
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*/
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data = ast_p_nand_casdo_read((u8)addr);
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- return data ;
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+ return data;
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}
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/*
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@@ -1587,7 +1587,7 @@ static inline bool prep_for_next_xfer(cy_as_hal_device_tag tag, uint8_t ep)
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static void cy_service_e_p_dma_read_request(
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cy_as_omap_dev_kernel *dev_p, uint8_t ep)
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{
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- cy_as_hal_device_tag tag = (cy_as_hal_device_tag)dev_p ;
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+ cy_as_hal_device_tag tag = (cy_as_hal_device_tag)dev_p;
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uint16_t v, size;
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void *dptr;
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uint16_t col_addr = 0x0000;
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@@ -1628,7 +1628,7 @@ static void cy_service_e_p_dma_read_request(
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/*
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* clear DMAVALID bit indicating that the data has been read
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*/
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- cy_as_hal_write_register(tag, ep_dma_reg, 0) ;
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+ cy_as_hal_write_register(tag, ep_dma_reg, 0);
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end_points[ep].seg_xfer_cnt += size;
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end_points[ep].req_xfer_cnt += size;
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@@ -1646,12 +1646,12 @@ static void cy_service_e_p_dma_read_request(
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* data we are going to xfer next
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*/
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v = end_points[ep].dma_xfer_sz/*HAL_DMA_PKT_SZ*/ |
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- CY_AS_MEM_P0_E_pn_DMA_REG_DMAVAL ;
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+ CY_AS_MEM_P0_E_pn_DMA_REG_DMAVAL;
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cy_as_hal_write_register(tag, ep_dma_reg, v);
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} else {
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- end_points[ep].pending = cy_false ;
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- end_points[ep].type = cy_as_hal_none ;
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- end_points[ep].buffer_valid = cy_false ;
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+ end_points[ep].pending = cy_false;
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+ end_points[ep].type = cy_as_hal_none;
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+ end_points[ep].buffer_valid = cy_false;
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/*
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* notify the API that we are done with rq on this EP
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@@ -1679,13 +1679,13 @@ static void cy_service_e_p_dma_write_request(
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uint32_t row_addr = CYAS_DEV_CALC_EP_ADDR(ep);
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void *dptr;
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- cy_as_hal_device_tag tag = (cy_as_hal_device_tag)dev_p ;
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+ cy_as_hal_device_tag tag = (cy_as_hal_device_tag)dev_p;
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/*
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* note: size here its the size of the dma transfer could be
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* anything > 0 && < P_PORT packet size
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*/
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- size = end_points[ep].dma_xfer_sz ;
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- dptr = end_points[ep].data_p ;
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+ size = end_points[ep].dma_xfer_sz;
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+ dptr = end_points[ep].data_p;
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/*
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* perform the soft DMA transfer, soft in this case
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@@ -1708,8 +1708,8 @@ static void cy_service_e_p_dma_write_request(
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* or used internally.
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*/
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- addr = CY_AS_MEM_P0_EP2_DMA_REG + ep - 2 ;
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- cy_as_hal_write_register(tag, addr, size) ;
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+ addr = CY_AS_MEM_P0_EP2_DMA_REG + ep - 2;
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+ cy_as_hal_write_register(tag, addr, size);
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/*
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* finally, tell the USB subsystem that the
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@@ -1721,13 +1721,13 @@ static void cy_service_e_p_dma_write_request(
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* There is more data to go. Re-init the WestBridge DMA side
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*/
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v = end_points[ep].dma_xfer_sz |
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- CY_AS_MEM_P0_E_pn_DMA_REG_DMAVAL ;
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- cy_as_hal_write_register(tag, addr, v) ;
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+ CY_AS_MEM_P0_E_pn_DMA_REG_DMAVAL;
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+ cy_as_hal_write_register(tag, addr, v);
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} else {
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- end_points[ep].pending = cy_false ;
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- end_points[ep].type = cy_as_hal_none ;
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- end_points[ep].buffer_valid = cy_false ;
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+ end_points[ep].pending = cy_false;
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+ end_points[ep].type = cy_as_hal_none;
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+ end_points[ep].buffer_valid = cy_false;
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/*
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* notify the API that we are done with rq on this EP
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@@ -1749,17 +1749,17 @@ static void cy_service_e_p_dma_write_request(
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*/
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static void cy_handle_d_r_q_interrupt(cy_as_omap_dev_kernel *dev_p)
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{
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- uint16_t v ;
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- static uint8_t service_ep = 2 ;
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+ uint16_t v;
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+ static uint8_t service_ep = 2;
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/*
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* We've got DRQ INT, read DRQ STATUS Register */
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v = cy_as_hal_read_register((cy_as_hal_device_tag)dev_p,
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- CY_AS_MEM_P0_DRQ) ;
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+ CY_AS_MEM_P0_DRQ);
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if (v == 0) {
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#ifndef WESTBRIDGE_NDEBUG
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- cy_as_hal_print_message("stray DRQ interrupt detected\n") ;
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+ cy_as_hal_print_message("stray DRQ interrupt detected\n");
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#endif
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return;
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}
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@@ -1773,9 +1773,9 @@ static void cy_handle_d_r_q_interrupt(cy_as_omap_dev_kernel *dev_p)
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while ((v & (1 << service_ep)) == 0) {
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if (service_ep == 15)
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- service_ep = 2 ;
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+ service_ep = 2;
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else
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- service_ep++ ;
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+ service_ep++;
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}
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if (end_points[service_ep].type == cy_as_hal_write) {
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@@ -1783,19 +1783,19 @@ static void cy_handle_d_r_q_interrupt(cy_as_omap_dev_kernel *dev_p)
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* handle DMA WRITE REQUEST: app_cpu will
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* write data into astoria EP buffer
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*/
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- cy_service_e_p_dma_write_request(dev_p, service_ep) ;
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+ cy_service_e_p_dma_write_request(dev_p, service_ep);
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} else if (end_points[service_ep].type == cy_as_hal_read) {
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/*
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* handle DMA READ REQUEST: cpu will
|
|
|
* read EP buffer from Astoria
|
|
|
*/
|
|
|
- cy_service_e_p_dma_read_request(dev_p, service_ep) ;
|
|
|
+ cy_service_e_p_dma_read_request(dev_p, service_ep);
|
|
|
}
|
|
|
#ifndef WESTBRIDGE_NDEBUG
|
|
|
else
|
|
|
cy_as_hal_print_message("cyashalomap:interrupt,"
|
|
|
" w/o pending DMA job,"
|
|
|
- "-check DRQ_MASK logic\n") ;
|
|
|
+ "-check DRQ_MASK logic\n");
|
|
|
#endif
|
|
|
|
|
|
/*
|
|
@@ -1804,9 +1804,9 @@ static void cy_handle_d_r_q_interrupt(cy_as_omap_dev_kernel *dev_p)
|
|
|
*/
|
|
|
if (end_points[service_ep].type == cy_as_hal_none) {
|
|
|
if (service_ep == 15)
|
|
|
- service_ep = 2 ;
|
|
|
+ service_ep = 2;
|
|
|
else
|
|
|
- service_ep++ ;
|
|
|
+ service_ep++;
|
|
|
}
|
|
|
|
|
|
}
|
|
@@ -1818,7 +1818,7 @@ void cy_as_hal_dma_cancel_request(cy_as_hal_device_tag tag, uint8_t ep)
|
|
|
cy_as_hal_write_register(tag,
|
|
|
CY_AS_MEM_P0_EP2_DMA_REG + ep - 2, 0);
|
|
|
|
|
|
- end_points[ep].buffer_valid = cy_false ;
|
|
|
+ end_points[ep].buffer_valid = cy_false;
|
|
|
end_points[ep].type = cy_as_hal_none;
|
|
|
}
|
|
|
|
|
@@ -1845,7 +1845,7 @@ void cy_as_hal_dma_setup_write(cy_as_hal_device_tag tag,
|
|
|
uint8_t ep, void *buf,
|
|
|
uint32_t size, uint16_t maxsize)
|
|
|
{
|
|
|
- uint32_t addr = 0 ;
|
|
|
+ uint32_t addr = 0;
|
|
|
uint16_t v = 0;
|
|
|
|
|
|
/*
|
|
@@ -1853,15 +1853,15 @@ void cy_as_hal_dma_setup_write(cy_as_hal_device_tag tag,
|
|
|
* "maxsize" - is the P port fragment size
|
|
|
* No EP0 or EP1 traffic should get here
|
|
|
*/
|
|
|
- cy_as_hal_assert(ep != 0 && ep != 1) ;
|
|
|
+ cy_as_hal_assert(ep != 0 && ep != 1);
|
|
|
|
|
|
/*
|
|
|
* If this asserts, we have an ordering problem. Another DMA request
|
|
|
* is coming down before the previous one has completed.
|
|
|
*/
|
|
|
- cy_as_hal_assert(end_points[ep].buffer_valid == cy_false) ;
|
|
|
- end_points[ep].buffer_valid = cy_true ;
|
|
|
- end_points[ep].type = cy_as_hal_write ;
|
|
|
+ cy_as_hal_assert(end_points[ep].buffer_valid == cy_false);
|
|
|
+ end_points[ep].buffer_valid = cy_true;
|
|
|
+ end_points[ep].type = cy_as_hal_write;
|
|
|
end_points[ep].pending = cy_true;
|
|
|
|
|
|
/*
|
|
@@ -1899,7 +1899,7 @@ void cy_as_hal_dma_setup_write(cy_as_hal_device_tag tag,
|
|
|
*/
|
|
|
end_points[ep].sg_p = buf;
|
|
|
end_points[ep].data_p = sg_virt(end_points[ep].sg_p);
|
|
|
- end_points[ep].seg_xfer_cnt = 0 ;
|
|
|
+ end_points[ep].seg_xfer_cnt = 0;
|
|
|
end_points[ep].req_xfer_cnt = 0;
|
|
|
|
|
|
#ifdef DBGPRN_DMA_SETUP_WR
|
|
@@ -1940,11 +1940,11 @@ void cy_as_hal_dma_setup_write(cy_as_hal_device_tag tag,
|
|
|
* Tell WB we are ready to send data on the given endpoint
|
|
|
*/
|
|
|
v = (end_points[ep].dma_xfer_sz & CY_AS_MEM_P0_E_pn_DMA_REG_COUNT_MASK)
|
|
|
- | CY_AS_MEM_P0_E_pn_DMA_REG_DMAVAL ;
|
|
|
+ | CY_AS_MEM_P0_E_pn_DMA_REG_DMAVAL;
|
|
|
|
|
|
- addr = CY_AS_MEM_P0_EP2_DMA_REG + ep - 2 ;
|
|
|
+ addr = CY_AS_MEM_P0_EP2_DMA_REG + ep - 2;
|
|
|
|
|
|
- cy_as_hal_write_register(tag, addr, v) ;
|
|
|
+ cy_as_hal_write_register(tag, addr, v);
|
|
|
}
|
|
|
|
|
|
/*
|
|
@@ -1957,15 +1957,15 @@ void cy_as_hal_dma_setup_read(cy_as_hal_device_tag tag,
|
|
|
uint8_t ep, void *buf,
|
|
|
uint32_t size, uint16_t maxsize)
|
|
|
{
|
|
|
- uint32_t addr ;
|
|
|
- uint16_t v ;
|
|
|
+ uint32_t addr;
|
|
|
+ uint16_t v;
|
|
|
|
|
|
/*
|
|
|
* Note: "size" is the actual request size
|
|
|
* "maxsize" - is the P port fragment size
|
|
|
* No EP0 or EP1 traffic should get here
|
|
|
*/
|
|
|
- cy_as_hal_assert(ep != 0 && ep != 1) ;
|
|
|
+ cy_as_hal_assert(ep != 0 && ep != 1);
|
|
|
|
|
|
/*
|
|
|
* If this asserts, we have an ordering problem.
|
|
@@ -1976,8 +1976,8 @@ void cy_as_hal_dma_setup_read(cy_as_hal_device_tag tag,
|
|
|
|
|
|
cy_as_hal_assert(end_points[ep].buffer_valid == cy_false);
|
|
|
|
|
|
- end_points[ep].buffer_valid = cy_true ;
|
|
|
- end_points[ep].type = cy_as_hal_read ;
|
|
|
+ end_points[ep].buffer_valid = cy_true;
|
|
|
+ end_points[ep].type = cy_as_hal_read;
|
|
|
end_points[ep].pending = cy_true;
|
|
|
end_points[ep].req_xfer_cnt = 0;
|
|
|
end_points[ep].req_length = size;
|
|
@@ -1996,7 +1996,7 @@ void cy_as_hal_dma_setup_read(cy_as_hal_device_tag tag,
|
|
|
end_points[ep].dma_xfer_sz = size;
|
|
|
}
|
|
|
|
|
|
- addr = CY_AS_MEM_P0_EP2_DMA_REG + ep - 2 ;
|
|
|
+ addr = CY_AS_MEM_P0_EP2_DMA_REG + ep - 2;
|
|
|
|
|
|
if (end_points[ep].sg_list_enabled) {
|
|
|
/*
|
|
@@ -2005,7 +2005,7 @@ void cy_as_hal_dma_setup_read(cy_as_hal_device_tag tag,
|
|
|
* buf - pointer to the SG list
|
|
|
* data_p - data pointer for the 1st DMA segment
|
|
|
*/
|
|
|
- end_points[ep].seg_xfer_cnt = 0 ;
|
|
|
+ end_points[ep].seg_xfer_cnt = 0;
|
|
|
end_points[ep].sg_p = buf;
|
|
|
end_points[ep].data_p = sg_virt(end_points[ep].sg_p);
|
|
|
|
|
@@ -2020,7 +2020,7 @@ void cy_as_hal_dma_setup_read(cy_as_hal_device_tag tag,
|
|
|
#endif
|
|
|
v = (end_points[ep].dma_xfer_sz &
|
|
|
CY_AS_MEM_P0_E_pn_DMA_REG_COUNT_MASK) |
|
|
|
- CY_AS_MEM_P0_E_pn_DMA_REG_DMAVAL ;
|
|
|
+ CY_AS_MEM_P0_E_pn_DMA_REG_DMAVAL;
|
|
|
cy_as_hal_write_register(tag, addr, v);
|
|
|
} else {
|
|
|
/*
|
|
@@ -2045,7 +2045,7 @@ void cy_as_hal_dma_setup_read(cy_as_hal_device_tag tag,
|
|
|
if (is_storage_e_p(ep)) {
|
|
|
v = (end_points[ep].dma_xfer_sz &
|
|
|
CY_AS_MEM_P0_E_pn_DMA_REG_COUNT_MASK) |
|
|
|
- CY_AS_MEM_P0_E_pn_DMA_REG_DMAVAL ;
|
|
|
+ CY_AS_MEM_P0_E_pn_DMA_REG_DMAVAL;
|
|
|
cy_as_hal_write_register(tag, addr, v);
|
|
|
}
|
|
|
}
|
|
@@ -2061,7 +2061,7 @@ void cy_as_hal_dma_register_callback(cy_as_hal_device_tag tag,
|
|
|
{
|
|
|
DBGPRN("<1>\n%s: WB API has registered a dma_complete callback:%x\n",
|
|
|
__func__, (uint32_t)cb);
|
|
|
- callback = cb ;
|
|
|
+ callback = cb;
|
|
|
}
|
|
|
|
|
|
/*
|
|
@@ -2106,14 +2106,14 @@ cy_bool cy_as_hal_set_wakeup_pin(cy_as_hal_device_tag tag, cy_bool state)
|
|
|
/*
|
|
|
* Not supported as of now.
|
|
|
*/
|
|
|
- return cy_false ;
|
|
|
+ return cy_false;
|
|
|
}
|
|
|
|
|
|
void cy_as_hal_pll_lock_loss_handler(cy_as_hal_device_tag tag)
|
|
|
{
|
|
|
- cy_as_hal_print_message("error: astoria PLL lock is lost\n") ;
|
|
|
+ cy_as_hal_print_message("error: astoria PLL lock is lost\n");
|
|
|
cy_as_hal_print_message("please check the input voltage levels");
|
|
|
- cy_as_hal_print_message("and clock, and restart the system\n") ;
|
|
|
+ cy_as_hal_print_message("and clock, and restart the system\n");
|
|
|
}
|
|
|
|
|
|
/*
|
|
@@ -2127,10 +2127,10 @@ void cy_as_hal_pll_lock_loss_handler(cy_as_hal_device_tag tag)
|
|
|
*/
|
|
|
void *cy_as_hal_alloc(uint32_t cnt)
|
|
|
{
|
|
|
- void *ret_p ;
|
|
|
+ void *ret_p;
|
|
|
|
|
|
- ret_p = kmalloc(cnt, GFP_ATOMIC) ;
|
|
|
- return ret_p ;
|
|
|
+ ret_p = kmalloc(cnt, GFP_ATOMIC);
|
|
|
+ return ret_p;
|
|
|
}
|
|
|
|
|
|
/*
|
|
@@ -2140,7 +2140,7 @@ void *cy_as_hal_alloc(uint32_t cnt)
|
|
|
*/
|
|
|
void cy_as_hal_free(void *mem_p)
|
|
|
{
|
|
|
- kfree(mem_p) ;
|
|
|
+ kfree(mem_p);
|
|
|
}
|
|
|
|
|
|
/*
|
|
@@ -2150,10 +2150,10 @@ void cy_as_hal_free(void *mem_p)
|
|
|
*/
|
|
|
void *cy_as_hal_c_b_alloc(uint32_t cnt)
|
|
|
{
|
|
|
- void *ret_p ;
|
|
|
+ void *ret_p;
|
|
|
|
|
|
- ret_p = kmalloc(cnt, GFP_ATOMIC) ;
|
|
|
- return ret_p ;
|
|
|
+ ret_p = kmalloc(cnt, GFP_ATOMIC);
|
|
|
+ return ret_p;
|
|
|
}
|
|
|
|
|
|
/*
|
|
@@ -2163,7 +2163,7 @@ void *cy_as_hal_c_b_alloc(uint32_t cnt)
|
|
|
*/
|
|
|
void cy_as_hal_mem_set(void *ptr, uint8_t value, uint32_t cnt)
|
|
|
{
|
|
|
- memset(ptr, value, cnt) ;
|
|
|
+ memset(ptr, value, cnt);
|
|
|
}
|
|
|
|
|
|
/*
|
|
@@ -2176,8 +2176,8 @@ void cy_as_hal_mem_set(void *ptr, uint8_t value, uint32_t cnt)
|
|
|
*/
|
|
|
cy_bool cy_as_hal_create_sleep_channel(cy_as_hal_sleep_channel *channel)
|
|
|
{
|
|
|
- init_waitqueue_head(&channel->wq) ;
|
|
|
- return cy_true ;
|
|
|
+ init_waitqueue_head(&channel->wq);
|
|
|
+ return cy_true;
|
|
|
}
|
|
|
|
|
|
/*
|
|
@@ -2187,7 +2187,7 @@ cy_bool cy_as_hal_create_sleep_channel(cy_as_hal_sleep_channel *channel)
|
|
|
*/
|
|
|
cy_bool cy_as_hal_destroy_sleep_channel(cy_as_hal_sleep_channel *channel)
|
|
|
{
|
|
|
- return cy_true ;
|
|
|
+ return cy_true;
|
|
|
}
|
|
|
|
|
|
/*
|
|
@@ -2195,8 +2195,8 @@ cy_bool cy_as_hal_destroy_sleep_channel(cy_as_hal_sleep_channel *channel)
|
|
|
*/
|
|
|
cy_bool cy_as_hal_sleep_on(cy_as_hal_sleep_channel *channel, uint32_t ms)
|
|
|
{
|
|
|
- wait_event_interruptible_timeout(channel->wq, 0, ((ms * HZ)/1000)) ;
|
|
|
- return cy_true ;
|
|
|
+ wait_event_interruptible_timeout(channel->wq, 0, ((ms * HZ)/1000));
|
|
|
+ return cy_true;
|
|
|
}
|
|
|
|
|
|
/*
|
|
@@ -2205,7 +2205,7 @@ cy_bool cy_as_hal_sleep_on(cy_as_hal_sleep_channel *channel, uint32_t ms)
|
|
|
cy_bool cy_as_hal_wake(cy_as_hal_sleep_channel *channel)
|
|
|
{
|
|
|
wake_up_interruptible_all(&channel->wq);
|
|
|
- return cy_true ;
|
|
|
+ return cy_true;
|
|
|
}
|
|
|
|
|
|
uint32_t cy_as_hal_disable_interrupts()
|
|
@@ -2213,13 +2213,13 @@ uint32_t cy_as_hal_disable_interrupts()
|
|
|
if (0 == intr__enable)
|
|
|
;
|
|
|
|
|
|
- intr__enable++ ;
|
|
|
- return 0 ;
|
|
|
+ intr__enable++;
|
|
|
+ return 0;
|
|
|
}
|
|
|
|
|
|
void cy_as_hal_enable_interrupts(uint32_t val)
|
|
|
{
|
|
|
- intr__enable-- ;
|
|
|
+ intr__enable--;
|
|
|
if (0 == intr__enable)
|
|
|
;
|
|
|
}
|
|
@@ -2240,9 +2240,9 @@ void cy_as_hal_sleep(uint32_t ms)
|
|
|
{
|
|
|
cy_as_hal_sleep_channel channel;
|
|
|
|
|
|
- cy_as_hal_create_sleep_channel(&channel) ;
|
|
|
- cy_as_hal_sleep_on(&channel, ms) ;
|
|
|
- cy_as_hal_destroy_sleep_channel(&channel) ;
|
|
|
+ cy_as_hal_create_sleep_channel(&channel);
|
|
|
+ cy_as_hal_sleep_on(&channel, ms);
|
|
|
+ cy_as_hal_destroy_sleep_channel(&channel);
|
|
|
}
|
|
|
|
|
|
cy_bool cy_as_hal_is_polling()
|
|
@@ -2287,7 +2287,7 @@ cy_bool cy_as_hal_sync_device_clocks(cy_as_hal_device_tag tag)
|
|
|
int start_o_m_a_p_kernel(const char *pgm,
|
|
|
cy_as_hal_device_tag *tag, cy_bool debug)
|
|
|
{
|
|
|
- cy_as_omap_dev_kernel *dev_p ;
|
|
|
+ cy_as_omap_dev_kernel *dev_p;
|
|
|
int i;
|
|
|
u16 data16[4];
|
|
|
u8 pncfg_reg;
|
|
@@ -2302,11 +2302,11 @@ int start_o_m_a_p_kernel(const char *pgm,
|
|
|
/*
|
|
|
* Initialize the HAL level endpoint DMA data.
|
|
|
*/
|
|
|
- for (i = 0 ; i < sizeof(end_points)/sizeof(end_points[0]) ; i++) {
|
|
|
- end_points[i].data_p = 0 ;
|
|
|
- end_points[i].pending = cy_false ;
|
|
|
- end_points[i].size = 0 ;
|
|
|
- end_points[i].type = cy_as_hal_none ;
|
|
|
+ for (i = 0; i < sizeof(end_points)/sizeof(end_points[0]); i++) {
|
|
|
+ end_points[i].data_p = 0;
|
|
|
+ end_points[i].pending = cy_false;
|
|
|
+ end_points[i].size = 0;
|
|
|
+ end_points[i].type = cy_as_hal_none;
|
|
|
end_points[i].sg_list_enabled = cy_false;
|
|
|
|
|
|
/*
|
|
@@ -2321,11 +2321,11 @@ int start_o_m_a_p_kernel(const char *pgm,
|
|
|
* allocate memory for OMAP HAL
|
|
|
*/
|
|
|
dev_p = (cy_as_omap_dev_kernel *)cy_as_hal_alloc(
|
|
|
- sizeof(cy_as_omap_dev_kernel)) ;
|
|
|
+ sizeof(cy_as_omap_dev_kernel));
|
|
|
if (dev_p == 0) {
|
|
|
cy_as_hal_print_message("out of memory allocating OMAP"
|
|
|
- "device structure\n") ;
|
|
|
- return 0 ;
|
|
|
+ "device structure\n");
|
|
|
+ return 0;
|
|
|
}
|
|
|
|
|
|
dev_p->m_sig = CY_AS_OMAP_KERNEL_HAL_SIG;
|
|
@@ -2403,11 +2403,11 @@ int start_o_m_a_p_kernel(const char *pgm,
|
|
|
"after cfg_wr:%4.4x\n\n",
|
|
|
data16[0], pncfg_reg, data16[1]);
|
|
|
|
|
|
- dev_p->thread_flag = 1 ;
|
|
|
- spin_lock_init(&int_lock) ;
|
|
|
- dev_p->m_next_p = m_omap_list_p ;
|
|
|
+ dev_p->thread_flag = 1;
|
|
|
+ spin_lock_init(&int_lock);
|
|
|
+ dev_p->m_next_p = m_omap_list_p;
|
|
|
|
|
|
- m_omap_list_p = dev_p ;
|
|
|
+ m_omap_list_p = dev_p;
|
|
|
*tag = dev_p;
|
|
|
|
|
|
cy_as_hal_configure_interrupts((void *)dev_p);
|
|
@@ -2421,7 +2421,7 @@ int start_o_m_a_p_kernel(const char *pgm,
|
|
|
cy_as_hal_set_ep_dma_mode(4, true);
|
|
|
cy_as_hal_set_ep_dma_mode(8, true);
|
|
|
|
|
|
- return 1 ;
|
|
|
+ return 1;
|
|
|
|
|
|
/*
|
|
|
* there's been a NAND bus access error or
|
|
@@ -2433,7 +2433,7 @@ bus_acc_error:
|
|
|
* so the device will not call omap_stop
|
|
|
*/
|
|
|
cy_as_hal_omap_hardware_deinit(dev_p);
|
|
|
- cy_as_hal_free(dev_p) ;
|
|
|
+ cy_as_hal_free(dev_p);
|
|
|
return 0;
|
|
|
}
|
|
|
|