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@@ -37,6 +37,8 @@
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AR_2040_##_index : 0) \
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|((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \
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AR_GI##_index : 0) \
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+ |((_series)[_index].RateFlags & ATH9K_RATESERIES_STBC ? \
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+ AR_STBC##_index : 0) \
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|SM((_series)[_index].ChSel, AR_ChainSel##_index))
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#define CCK_SIFS_TIME 10
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@@ -434,7 +436,10 @@ struct ar5416_desc {
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#define AR_ChainSel3_S 17
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#define AR_RTSCTSRate 0x0ff00000
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#define AR_RTSCTSRate_S 20
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-#define AR_TxCtlRsvd70 0xf0000000
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+#define AR_STBC0 0x10000000
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+#define AR_STBC1 0x20000000
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+#define AR_STBC2 0x40000000
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+#define AR_STBC3 0x80000000
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#define AR_TxRSSIAnt00 0x000000ff
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#define AR_TxRSSIAnt00_S 0
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@@ -647,6 +652,7 @@ enum ath9k_rx_filter {
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#define ATH9K_RATESERIES_RTS_CTS 0x0001
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#define ATH9K_RATESERIES_2040 0x0002
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#define ATH9K_RATESERIES_HALFGI 0x0004
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+#define ATH9K_RATESERIES_STBC 0x0008
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struct ath9k_11n_rate_series {
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u32 Tries;
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