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@@ -938,6 +938,10 @@ int of_node_to_nid(struct device_node *dp)
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int count, nid;
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u64 grp;
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+ /* This is the right thing to do on currently supported
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+ * SUN4U NUMA platforms as well, as the PCI controller does
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+ * not sit behind any particular memory controller.
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+ */
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if (!mlgroups)
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return -1;
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@@ -1206,8 +1210,44 @@ out:
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return err;
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}
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+static int __init numa_parse_jbus(void)
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+{
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+ unsigned long cpu, index;
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+
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+ /* NUMA node id is encoded in bits 36 and higher, and there is
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+ * a 1-to-1 mapping from CPU ID to NUMA node ID.
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+ */
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+ index = 0;
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+ for_each_present_cpu(cpu) {
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+ numa_cpu_lookup_table[cpu] = index;
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+ numa_cpumask_lookup_table[index] = cpumask_of_cpu(cpu);
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+ node_masks[index].mask = ~((1UL << 36UL) - 1UL);
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+ node_masks[index].val = cpu << 36UL;
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+
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+ index++;
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+ }
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+ num_node_masks = index;
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+
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+ add_node_ranges();
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+
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+ for (index = 0; index < num_node_masks; index++) {
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+ allocate_node_data(index);
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+ node_set_online(index);
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+ }
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+
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+ return 0;
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+}
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+
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static int __init numa_parse_sun4u(void)
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{
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+ if (tlb_type == cheetah || tlb_type == cheetah_plus) {
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+ unsigned long ver;
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+
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+ __asm__ ("rdpr %%ver, %0" : "=r" (ver));
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+ if ((ver >> 32UL) == __JALAPENO_ID ||
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+ (ver >> 32UL) == __SERRANO_ID)
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+ return numa_parse_jbus();
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+ }
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return -1;
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}
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