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@@ -110,9 +110,12 @@
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#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
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#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
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-#define ADSP2_CONTROL 0
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-#define ADSP2_CLOCKING 1
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-#define ADSP2_STATUS1 4
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+#define ADSP2_CONTROL 0x0
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+#define ADSP2_CLOCKING 0x1
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+#define ADSP2_STATUS1 0x4
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+#define ADSP2_WDMA_CONFIG_1 0x30
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+#define ADSP2_WDMA_CONFIG_2 0x31
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+#define ADSP2_RDMA_CONFIG_1 0x34
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/*
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* ADSP2 Control
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@@ -688,7 +691,7 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp)
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hdr = (void*)&firmware->data[0];
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if (memcmp(hdr->magic, "WMDR", 4) != 0) {
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adsp_err(dsp, "%s: invalid magic\n", file);
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- return -EINVAL;
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+ goto out_fw;
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}
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switch (be32_to_cpu(hdr->rev) & 0xff) {
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@@ -1027,6 +1030,11 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w,
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ADSP2_SYS_ENA | ADSP2_CORE_ENA |
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ADSP2_START, 0);
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+ /* Make sure DMAs are quiesced */
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+ regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
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+ regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
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+ regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
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+
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if (dsp->dvfs) {
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ret = regulator_set_voltage(dsp->dvfs, 1200000,
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1800000);
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