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@@ -767,6 +767,7 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream,
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int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
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int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
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u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
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u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
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u16 pll_d = 1;
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u16 pll_d = 1;
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+ u8 reg;
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/* select data word length */
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/* select data word length */
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data =
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data =
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@@ -801,8 +802,16 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream,
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pll_q &= 0xf;
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pll_q &= 0xf;
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aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
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aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
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aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
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aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
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- } else
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+ /* disable PLL if it is bypassed */
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+ reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
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+ aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
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+
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+ } else {
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aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
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aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
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+ /* enable PLL when it is used */
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+ reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
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+ aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
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+ }
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/* Route Left DAC to left channel input and
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/* Route Left DAC to left channel input and
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* right DAC to right channel input */
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* right DAC to right channel input */
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