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@@ -49,7 +49,7 @@ void __iomem *omap4_get_scu_base(void)
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return scu_base;
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}
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-void __cpuinit platform_secondary_init(unsigned int cpu)
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+static void __cpuinit omap4_secondary_init(unsigned int cpu)
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{
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/*
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* Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
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@@ -77,7 +77,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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spin_unlock(&boot_lock);
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}
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-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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+static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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static struct clockdomain *cpu1_clkdm;
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static bool booted;
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@@ -165,7 +165,7 @@ static void __init wakeup_secondary(void)
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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-void __init smp_init_cpus(void)
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+static void __init omap4_smp_init_cpus(void)
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{
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unsigned int i = 0, ncores = 1, cpu_id;
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@@ -196,7 +196,7 @@ void __init smp_init_cpus(void)
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set_smp_cross_call(gic_raise_softirq);
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}
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-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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+static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
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{
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/*
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@@ -207,3 +207,13 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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scu_enable(scu_base);
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wakeup_secondary();
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}
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+
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+struct smp_operations omap4_smp_ops __initdata = {
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+ .smp_init_cpus = omap4_smp_init_cpus,
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+ .smp_prepare_cpus = omap4_smp_prepare_cpus,
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+ .smp_secondary_init = omap4_secondary_init,
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+ .smp_boot_secondary = omap4_boot_secondary,
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+#ifdef CONFIG_HOTPLUG_CPU
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+ .cpu_die = omap4_cpu_die,
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+#endif
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+};
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