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@@ -90,7 +90,7 @@ void mxr_reg_reset(struct mxr_device *mdev)
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mxr_vsync_set_update(mdev, MXR_DISABLE);
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/* set output in RGB888 mode */
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- mxr_write(mdev, MXR_CFG, MXR_CFG_OUT_YUV444);
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+ mxr_write(mdev, MXR_CFG, MXR_CFG_OUT_RGB888);
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/* 16 beat burst in DMA */
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mxr_write_mask(mdev, MXR_STATUS, MXR_STATUS_16_BURST,
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@@ -376,6 +376,12 @@ void mxr_reg_set_mbus_fmt(struct mxr_device *mdev,
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spin_lock_irqsave(&mdev->reg_slock, flags);
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mxr_vsync_set_update(mdev, MXR_DISABLE);
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+ /* selecting colorspace accepted by output */
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+ if (fmt->colorspace == V4L2_COLORSPACE_JPEG)
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+ val |= MXR_CFG_OUT_YUV444;
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+ else
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+ val |= MXR_CFG_OUT_RGB888;
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+
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/* choosing between interlace and progressive mode */
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if (fmt->field == V4L2_FIELD_INTERLACED)
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val |= MXR_CFG_SCAN_INTERLACE;
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@@ -394,7 +400,8 @@ void mxr_reg_set_mbus_fmt(struct mxr_device *mdev,
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else
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WARN(1, "unrecognized mbus height %u!\n", fmt->height);
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- mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_SCAN_MASK);
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+ mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_SCAN_MASK |
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+ MXR_CFG_OUT_MASK);
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val = (fmt->field == V4L2_FIELD_INTERLACED) ? ~0 : 0;
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vp_write_mask(mdev, VP_MODE, val,
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