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@@ -32,6 +32,8 @@
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#include <plat/cpu.h>
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+#include "common.h"
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+
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extern void exynos4_secondary_startup(void);
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#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
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@@ -64,7 +66,7 @@ static void __iomem *scu_base_addr(void)
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static DEFINE_SPINLOCK(boot_lock);
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-void __cpuinit platform_secondary_init(unsigned int cpu)
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+static void __cpuinit exynos_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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@@ -86,7 +88,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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spin_unlock(&boot_lock);
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}
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-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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+static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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@@ -161,7 +163,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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* which may be present or become present in the system.
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*/
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-void __init smp_init_cpus(void)
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+static void __init exynos_smp_init_cpus(void)
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{
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void __iomem *scu_base = scu_base_addr();
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unsigned int i, ncores;
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@@ -184,7 +186,7 @@ void __init smp_init_cpus(void)
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set_smp_cross_call(gic_raise_softirq);
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}
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-void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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+static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
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{
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if (!soc_is_exynos5250())
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scu_enable(scu_base_addr());
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@@ -198,3 +200,13 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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__raw_writel(virt_to_phys(exynos4_secondary_startup),
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CPU1_BOOT_REG);
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}
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+
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+struct smp_operations exynos_smp_ops __initdata = {
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+ .smp_init_cpus = exynos_smp_init_cpus,
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+ .smp_prepare_cpus = exynos_smp_prepare_cpus,
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+ .smp_secondary_init = exynos_secondary_init,
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+ .smp_boot_secondary = exynos_boot_secondary,
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+#ifdef CONFIG_HOTPLUG_CPU
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+ .cpu_die = exynos_cpu_die,
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+#endif
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+};
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