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Blackfin: SMP: kgdb: flush core internal write buffer before flushinv

KGDB single step in SMP kernel may hang forever in flushinv without a
CSYNC ahead.  This is because the core internal write buffers need to
be flushed before invalidating the data cache to make sure the insn
fetch is not out of sync.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Sonic Zhang 14 years ago
parent
commit
064cc44e62
1 changed files with 5 additions and 0 deletions
  1. 5 0
      arch/blackfin/mach-bf561/atomic.S

+ 5 - 0
arch/blackfin/mach-bf561/atomic.S

@@ -49,6 +49,7 @@ ENTRY(_get_core_lock)
 	jump .Lretry_corelock
 	jump .Lretry_corelock
 .Ldone_corelock:
 .Ldone_corelock:
 	p0 = r1;
 	p0 = r1;
+	/* flush core internal write buffer before invalidate dcache */
 	CSYNC(r2);
 	CSYNC(r2);
 	flushinv[p0];
 	flushinv[p0];
 	SSYNC(r2);
 	SSYNC(r2);
@@ -685,6 +686,8 @@ ENTRY(___raw_atomic_test_asm)
 	r1 = -L1_CACHE_BYTES;
 	r1 = -L1_CACHE_BYTES;
 	r1 = r0 & r1;
 	r1 = r0 & r1;
 	p0 = r1;
 	p0 = r1;
+	/* flush core internal write buffer before invalidate dcache */
+	CSYNC(r2);
 	flushinv[p0];
 	flushinv[p0];
 	SSYNC(r2);
 	SSYNC(r2);
 	r0 = [p1];
 	r0 = [p1];
@@ -907,6 +910,8 @@ ENTRY(___raw_uncached_fetch_asm)
 	r1 = -L1_CACHE_BYTES;
 	r1 = -L1_CACHE_BYTES;
 	r1 = r0 & r1;
 	r1 = r0 & r1;
 	p0 = r1;
 	p0 = r1;
+	/* flush core internal write buffer before invalidate dcache */
+	CSYNC(r2);
 	flushinv[p0];
 	flushinv[p0];
 	SSYNC(r2);
 	SSYNC(r2);
 	r0 = [p1];
 	r0 = [p1];