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@@ -461,8 +461,15 @@ void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
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}
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}
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+/* Updates Link Status for USB 2.1 port */
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+static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
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+{
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+ if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
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+ *status |= USB_PORT_STAT_L1;
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+}
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+
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/* Updates Link Status for super Speed port */
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-static void xhci_hub_report_link_state(u32 *status, u32 status_reg)
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+static void xhci_hub_report_usb3_link_state(u32 *status, u32 status_reg)
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{
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u32 pls = status_reg & PORT_PLS_MASK;
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@@ -631,14 +638,16 @@ static u32 xhci_get_port_status(struct usb_hcd *hcd,
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else
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status |= USB_PORT_STAT_POWER;
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}
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- /* Update Port Link State for super speed ports*/
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+ /* Update Port Link State */
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if (hcd->speed == HCD_USB3) {
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- xhci_hub_report_link_state(&status, raw_port_status);
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+ xhci_hub_report_usb3_link_state(&status, raw_port_status);
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/*
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* Verify if all USB3 Ports Have entered U0 already.
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* Delete Compliance Mode Timer if so.
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*/
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xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
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+ } else {
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+ xhci_hub_report_usb2_link_state(&status, raw_port_status);
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}
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if (bus_state->port_c_suspend & (1 << wIndex))
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status |= 1 << USB_PORT_FEAT_C_SUSPEND;
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