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@@ -26,6 +26,7 @@
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#include <asm/gpio.h>
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#include <asm/irq_handler.h>
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#include <asm/dpmc.h>
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+#include <asm/traps.h>
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#ifndef SEC_GCTL
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# define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
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@@ -413,6 +414,34 @@ void handle_sec_fault(unsigned int irq, struct irq_desc *desc)
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raw_spin_unlock(&desc->lock);
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}
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+void handle_core_fault(unsigned int irq, struct irq_desc *desc)
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+{
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+ struct pt_regs *fp = get_irq_regs();
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+
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+ raw_spin_lock(&desc->lock);
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+
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+ switch (irq) {
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+ case IRQ_C0_DBL_FAULT:
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+ double_fault_c(fp);
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+ break;
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+ case IRQ_C0_HW_ERR:
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+ dump_bfin_process(fp);
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+ dump_bfin_mem(fp);
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+ show_regs(fp);
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+ printk(KERN_NOTICE "Kernel Stack\n");
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+ show_stack(current, NULL);
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+ print_modules();
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+ panic("Kernel core hardware error");
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+ break;
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+ case IRQ_C0_NMI_L1_PARITY_ERR:
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+ panic("NMI %d occurs unexpectedly");
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+ break;
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+ default:
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+ panic("Core 1 fault %d occurs unexpectedly");
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+ }
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+
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+ raw_spin_unlock(&desc->lock);
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+}
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#endif
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#ifdef CONFIG_SMP
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@@ -1522,9 +1551,12 @@ int __init init_arch_irq(void)
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} else if (irq < BFIN_IRQ(0)) {
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irq_set_chip_and_handler(irq, &bfin_internal_irqchip,
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handle_simple_irq);
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- } else if (irq < CORE_IRQS && irq != IRQ_CGU_EVT) {
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+ } else if (irq == IRQ_SEC_ERR) {
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irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
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handle_sec_fault);
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+ } else if (irq < CORE_IRQS && irq >= IRQ_C0_DBL_FAULT) {
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+ irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
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+ handle_core_fault);
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} else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) {
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irq_set_chip(irq, &bfin_sec_irqchip);
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irq_set_chained_handler(irq, bfin_demux_gpio_irq);
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