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@@ -50,6 +50,7 @@
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((((bus)<<16) | ((devfunc)<<8) | (offset & 0xfc)) + tsi108_pci_cfg_base)
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u32 tsi108_pci_cfg_base;
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+static u32 tsi108_pci_cfg_phys;
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u32 tsi108_csr_vir_base;
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static struct device_node *pci_irq_node;
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static struct irq_host *pci_irq_host;
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@@ -186,7 +187,7 @@ tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
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void tsi108_clear_pci_cfg_error(void)
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{
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- tsi108_clear_pci_error(TSI108_PCI_CFG_BASE_PHYS);
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+ tsi108_clear_pci_error(tsi108_pci_cfg_phys);
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}
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static struct pci_ops tsi108_direct_pci_ops = {
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@@ -194,17 +195,17 @@ static struct pci_ops tsi108_direct_pci_ops = {
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tsi108_direct_write_config
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};
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-int __init tsi108_setup_pci(struct device_node *dev)
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+int __init tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary)
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{
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int len;
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struct pci_controller *hose;
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struct resource rsrc;
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const int *bus_range;
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- int primary = 0, has_address = 0;
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+ int has_address = 0;
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/* PCI Config mapping */
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- tsi108_pci_cfg_base = (u32)ioremap(TSI108_PCI_CFG_BASE_PHYS,
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- TSI108_PCI_CFG_SIZE);
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+ tsi108_pci_cfg_base = (u32)ioremap(cfg_phys, TSI108_PCI_CFG_SIZE);
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+ tsi108_pci_cfg_phys = cfg_phys;
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DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __FUNCTION__,
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tsi108_pci_cfg_base);
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