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@@ -1,562 +0,0 @@
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-/*
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- * hw_mmu.c
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- *
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- * DSP-BIOS Bridge driver support functions for TI OMAP processors.
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- *
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- * API definitions to setup MMU TLB and PTE
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- *
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- * Copyright (C) 2007 Texas Instruments, Inc.
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- *
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- * This package is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
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- * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
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- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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- */
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-
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-#include <linux/io.h>
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-#include "MMURegAcM.h"
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-#include <hw_defs.h>
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-#include <hw_mmu.h>
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-#include <linux/types.h>
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-#include <linux/err.h>
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-
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-#define MMU_BASE_VAL_MASK 0xFC00
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-#define MMU_PAGE_MAX 3
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-#define MMU_ELEMENTSIZE_MAX 3
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-#define MMU_ADDR_MASK 0xFFFFF000
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-#define MMU_TTB_MASK 0xFFFFC000
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-#define MMU_SECTION_ADDR_MASK 0xFFF00000
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-#define MMU_SSECTION_ADDR_MASK 0xFF000000
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-#define MMU_PAGE_TABLE_MASK 0xFFFFFC00
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-#define MMU_LARGE_PAGE_MASK 0xFFFF0000
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-#define MMU_SMALL_PAGE_MASK 0xFFFFF000
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-
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-#define MMU_LOAD_TLB 0x00000001
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-#define MMU_GFLUSH 0x60
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-
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-/*
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- * hw_mmu_page_size_t: Enumerated Type used to specify the MMU Page Size(SLSS)
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- */
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-enum hw_mmu_page_size_t {
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- HW_MMU_SECTION,
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- HW_MMU_LARGE_PAGE,
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- HW_MMU_SMALL_PAGE,
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- HW_MMU_SUPERSECTION
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-};
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-
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-/*
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- * FUNCTION : mmu_flush_entry
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- *
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- * INPUTS:
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- *
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- * Identifier : base_address
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- * Type : const u32
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- * Description : Base Address of instance of MMU module
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- *
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- * RETURNS:
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- *
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- * Type : hw_status
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- * Description : 0 -- No errors occured
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- * RET_BAD_NULL_PARAM -- A Pointer
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- * Paramater was set to NULL
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- *
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- * PURPOSE: : Flush the TLB entry pointed by the
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- * lock counter register
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- * even if this entry is set protected
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- *
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- * METHOD: : Check the Input parameter and Flush a
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- * single entry in the TLB.
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- */
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-static hw_status mmu_flush_entry(const void __iomem *base_address);
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-
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-/*
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- * FUNCTION : mmu_set_cam_entry
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- *
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- * INPUTS:
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- *
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- * Identifier : base_address
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- * TypE : const u32
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- * Description : Base Address of instance of MMU module
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- *
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- * Identifier : page_sz
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- * TypE : const u32
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- * Description : It indicates the page size
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- *
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- * Identifier : preserved_bit
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- * Type : const u32
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- * Description : It indicates the TLB entry is preserved entry
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- * or not
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- *
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- * Identifier : valid_bit
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- * Type : const u32
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- * Description : It indicates the TLB entry is valid entry or not
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- *
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- *
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- * Identifier : virtual_addr_tag
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- * Type : const u32
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- * Description : virtual Address
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- *
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- * RETURNS:
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- *
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- * Type : hw_status
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- * Description : 0 -- No errors occured
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- * RET_BAD_NULL_PARAM -- A Pointer Paramater
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- * was set to NULL
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- * RET_PARAM_OUT_OF_RANGE -- Input Parameter out
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- * of Range
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- *
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- * PURPOSE: : Set MMU_CAM reg
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- *
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- * METHOD: : Check the Input parameters and set the CAM entry.
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- */
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-static hw_status mmu_set_cam_entry(const void __iomem *base_address,
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- const u32 page_sz,
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- const u32 preserved_bit,
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- const u32 valid_bit,
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- const u32 virtual_addr_tag);
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-
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-/*
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- * FUNCTION : mmu_set_ram_entry
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- *
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- * INPUTS:
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- *
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- * Identifier : base_address
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- * Type : const u32
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- * Description : Base Address of instance of MMU module
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- *
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- * Identifier : physical_addr
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- * Type : const u32
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- * Description : Physical Address to which the corresponding
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- * virtual Address shouldpoint
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- *
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- * Identifier : endianism
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- * Type : hw_endianism_t
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- * Description : endianism for the given page
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- *
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- * Identifier : element_size
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- * Type : hw_element_size_t
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- * Description : The element size ( 8,16, 32 or 64 bit)
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- *
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- * Identifier : mixed_size
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- * Type : hw_mmu_mixed_size_t
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- * Description : Element Size to follow CPU or TLB
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- *
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- * RETURNS:
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- *
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- * Type : hw_status
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- * Description : 0 -- No errors occured
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- * RET_BAD_NULL_PARAM -- A Pointer Paramater
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- * was set to NULL
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- * RET_PARAM_OUT_OF_RANGE -- Input Parameter
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- * out of Range
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- *
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- * PURPOSE: : Set MMU_CAM reg
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- *
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- * METHOD: : Check the Input parameters and set the RAM entry.
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- */
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-static hw_status mmu_set_ram_entry(const void __iomem *base_address,
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- const u32 physical_addr,
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- enum hw_endianism_t endianism,
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- enum hw_element_size_t element_size,
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- enum hw_mmu_mixed_size_t mixed_size);
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-
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-/* HW FUNCTIONS */
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-
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-hw_status hw_mmu_enable(const void __iomem *base_address)
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-{
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- hw_status status = 0;
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-
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- MMUMMU_CNTLMMU_ENABLE_WRITE32(base_address, HW_SET);
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-
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- return status;
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-}
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-
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-hw_status hw_mmu_disable(const void __iomem *base_address)
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-{
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- hw_status status = 0;
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-
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- MMUMMU_CNTLMMU_ENABLE_WRITE32(base_address, HW_CLEAR);
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-
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- return status;
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-}
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-
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-hw_status hw_mmu_num_locked_set(const void __iomem *base_address,
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- u32 num_locked_entries)
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-{
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- hw_status status = 0;
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-
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- MMUMMU_LOCK_BASE_VALUE_WRITE32(base_address, num_locked_entries);
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-
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- return status;
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-}
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-
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-hw_status hw_mmu_victim_num_set(const void __iomem *base_address,
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- u32 victim_entry_num)
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-{
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- hw_status status = 0;
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-
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- MMUMMU_LOCK_CURRENT_VICTIM_WRITE32(base_address, victim_entry_num);
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-
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- return status;
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-}
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-
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-hw_status hw_mmu_event_ack(const void __iomem *base_address, u32 irq_mask)
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-{
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- hw_status status = 0;
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-
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- MMUMMU_IRQSTATUS_WRITE_REGISTER32(base_address, irq_mask);
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-
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- return status;
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-}
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-
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-hw_status hw_mmu_event_disable(const void __iomem *base_address, u32 irq_mask)
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-{
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- hw_status status = 0;
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- u32 irq_reg;
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-
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- irq_reg = MMUMMU_IRQENABLE_READ_REGISTER32(base_address);
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-
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- MMUMMU_IRQENABLE_WRITE_REGISTER32(base_address, irq_reg & ~irq_mask);
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-
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- return status;
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-}
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-
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-hw_status hw_mmu_event_enable(const void __iomem *base_address, u32 irq_mask)
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-{
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- hw_status status = 0;
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- u32 irq_reg;
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-
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- irq_reg = MMUMMU_IRQENABLE_READ_REGISTER32(base_address);
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-
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- MMUMMU_IRQENABLE_WRITE_REGISTER32(base_address, irq_reg | irq_mask);
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-
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- return status;
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-}
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-
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-hw_status hw_mmu_event_status(const void __iomem *base_address, u32 *irq_mask)
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-{
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- hw_status status = 0;
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-
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- *irq_mask = MMUMMU_IRQSTATUS_READ_REGISTER32(base_address);
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-
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- return status;
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-}
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-
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-hw_status hw_mmu_fault_addr_read(const void __iomem *base_address, u32 *addr)
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-{
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- hw_status status = 0;
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-
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- /* read values from register */
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- *addr = MMUMMU_FAULT_AD_READ_REGISTER32(base_address);
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-
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- return status;
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-}
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-
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-hw_status hw_mmu_ttb_set(const void __iomem *base_address, u32 ttb_phys_addr)
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-{
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- hw_status status = 0;
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- u32 load_ttb;
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-
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- load_ttb = ttb_phys_addr & ~0x7FUL;
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- /* write values to register */
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- MMUMMU_TTB_WRITE_REGISTER32(base_address, load_ttb);
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-
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- return status;
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-}
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-
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-hw_status hw_mmu_twl_enable(const void __iomem *base_address)
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-{
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- hw_status status = 0;
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-
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- MMUMMU_CNTLTWL_ENABLE_WRITE32(base_address, HW_SET);
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-
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- return status;
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-}
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-
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-hw_status hw_mmu_twl_disable(const void __iomem *base_address)
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-{
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- hw_status status = 0;
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-
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- MMUMMU_CNTLTWL_ENABLE_WRITE32(base_address, HW_CLEAR);
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-
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- return status;
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-}
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-
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-hw_status hw_mmu_tlb_flush(const void __iomem *base_address, u32 virtual_addr,
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- u32 page_sz)
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-{
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- hw_status status = 0;
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- u32 virtual_addr_tag;
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- enum hw_mmu_page_size_t pg_size_bits;
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-
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- switch (page_sz) {
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- case HW_PAGE_SIZE4KB:
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- pg_size_bits = HW_MMU_SMALL_PAGE;
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- break;
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-
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- case HW_PAGE_SIZE64KB:
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- pg_size_bits = HW_MMU_LARGE_PAGE;
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- break;
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-
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- case HW_PAGE_SIZE1MB:
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- pg_size_bits = HW_MMU_SECTION;
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- break;
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-
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- case HW_PAGE_SIZE16MB:
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- pg_size_bits = HW_MMU_SUPERSECTION;
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- break;
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-
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- default:
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- return -EINVAL;
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- }
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-
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- /* Generate the 20-bit tag from virtual address */
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- virtual_addr_tag = ((virtual_addr & MMU_ADDR_MASK) >> 12);
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-
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- mmu_set_cam_entry(base_address, pg_size_bits, 0, 0, virtual_addr_tag);
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-
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- mmu_flush_entry(base_address);
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-
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- return status;
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-}
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-
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-hw_status hw_mmu_tlb_add(const void __iomem *base_address,
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- u32 physical_addr,
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- u32 virtual_addr,
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- u32 page_sz,
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- u32 entry_num,
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- struct hw_mmu_map_attrs_t *map_attrs,
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- s8 preserved_bit, s8 valid_bit)
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-{
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- hw_status status = 0;
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- u32 lock_reg;
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- u32 virtual_addr_tag;
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- enum hw_mmu_page_size_t mmu_pg_size;
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-
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- /*Check the input Parameters */
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- switch (page_sz) {
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- case HW_PAGE_SIZE4KB:
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- mmu_pg_size = HW_MMU_SMALL_PAGE;
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- break;
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-
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- case HW_PAGE_SIZE64KB:
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- mmu_pg_size = HW_MMU_LARGE_PAGE;
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- break;
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-
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- case HW_PAGE_SIZE1MB:
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- mmu_pg_size = HW_MMU_SECTION;
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- break;
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-
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- case HW_PAGE_SIZE16MB:
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- mmu_pg_size = HW_MMU_SUPERSECTION;
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- break;
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-
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- default:
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- return -EINVAL;
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- }
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-
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- lock_reg = MMUMMU_LOCK_READ_REGISTER32(base_address);
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-
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- /* Generate the 20-bit tag from virtual address */
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- virtual_addr_tag = ((virtual_addr & MMU_ADDR_MASK) >> 12);
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-
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- /* Write the fields in the CAM Entry Register */
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- mmu_set_cam_entry(base_address, mmu_pg_size, preserved_bit, valid_bit,
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- virtual_addr_tag);
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-
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- /* Write the different fields of the RAM Entry Register */
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- /* endianism of the page,Element Size of the page (8, 16, 32, 64 bit) */
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- mmu_set_ram_entry(base_address, physical_addr, map_attrs->endianism,
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- map_attrs->element_size, map_attrs->mixed_size);
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-
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- /* Update the MMU Lock Register */
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- /* currentVictim between lockedBaseValue and (MMU_Entries_Number - 1) */
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- MMUMMU_LOCK_CURRENT_VICTIM_WRITE32(base_address, entry_num);
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-
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- /* Enable loading of an entry in TLB by writing 1
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- into LD_TLB_REG register */
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- MMUMMU_LD_TLB_WRITE_REGISTER32(base_address, MMU_LOAD_TLB);
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-
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- MMUMMU_LOCK_WRITE_REGISTER32(base_address, lock_reg);
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-
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- return status;
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-}
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-
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-hw_status hw_mmu_pte_set(const u32 pg_tbl_va,
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- u32 physical_addr,
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- u32 virtual_addr,
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- u32 page_sz, struct hw_mmu_map_attrs_t *map_attrs)
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-{
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- hw_status status = 0;
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- u32 pte_addr, pte_val;
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- s32 num_entries = 1;
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-
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- switch (page_sz) {
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- case HW_PAGE_SIZE4KB:
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- pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va,
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- virtual_addr &
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- MMU_SMALL_PAGE_MASK);
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- pte_val =
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- ((physical_addr & MMU_SMALL_PAGE_MASK) |
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- (map_attrs->endianism << 9) | (map_attrs->
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- element_size << 4) |
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- (map_attrs->mixed_size << 11) | 2);
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- break;
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-
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- case HW_PAGE_SIZE64KB:
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- num_entries = 16;
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- pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va,
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- virtual_addr &
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- MMU_LARGE_PAGE_MASK);
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- pte_val =
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- ((physical_addr & MMU_LARGE_PAGE_MASK) |
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- (map_attrs->endianism << 9) | (map_attrs->
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- element_size << 4) |
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- (map_attrs->mixed_size << 11) | 1);
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- break;
|
|
|
-
|
|
|
- case HW_PAGE_SIZE1MB:
|
|
|
- pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va,
|
|
|
- virtual_addr &
|
|
|
- MMU_SECTION_ADDR_MASK);
|
|
|
- pte_val =
|
|
|
- ((((physical_addr & MMU_SECTION_ADDR_MASK) |
|
|
|
- (map_attrs->endianism << 15) | (map_attrs->
|
|
|
- element_size << 10) |
|
|
|
- (map_attrs->mixed_size << 17)) & ~0x40000) | 0x2);
|
|
|
- break;
|
|
|
-
|
|
|
- case HW_PAGE_SIZE16MB:
|
|
|
- num_entries = 16;
|
|
|
- pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va,
|
|
|
- virtual_addr &
|
|
|
- MMU_SSECTION_ADDR_MASK);
|
|
|
- pte_val =
|
|
|
- (((physical_addr & MMU_SSECTION_ADDR_MASK) |
|
|
|
- (map_attrs->endianism << 15) | (map_attrs->
|
|
|
- element_size << 10) |
|
|
|
- (map_attrs->mixed_size << 17)
|
|
|
- ) | 0x40000 | 0x2);
|
|
|
- break;
|
|
|
-
|
|
|
- case HW_MMU_COARSE_PAGE_SIZE:
|
|
|
- pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va,
|
|
|
- virtual_addr &
|
|
|
- MMU_SECTION_ADDR_MASK);
|
|
|
- pte_val = (physical_addr & MMU_PAGE_TABLE_MASK) | 1;
|
|
|
- break;
|
|
|
-
|
|
|
- default:
|
|
|
- return -EINVAL;
|
|
|
- }
|
|
|
-
|
|
|
- while (--num_entries >= 0)
|
|
|
- ((u32 *) pte_addr)[num_entries] = pte_val;
|
|
|
-
|
|
|
- return status;
|
|
|
-}
|
|
|
-
|
|
|
-hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, u32 virtual_addr, u32 page_size)
|
|
|
-{
|
|
|
- hw_status status = 0;
|
|
|
- u32 pte_addr;
|
|
|
- s32 num_entries = 1;
|
|
|
-
|
|
|
- switch (page_size) {
|
|
|
- case HW_PAGE_SIZE4KB:
|
|
|
- pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va,
|
|
|
- virtual_addr &
|
|
|
- MMU_SMALL_PAGE_MASK);
|
|
|
- break;
|
|
|
-
|
|
|
- case HW_PAGE_SIZE64KB:
|
|
|
- num_entries = 16;
|
|
|
- pte_addr = hw_mmu_pte_addr_l2(pg_tbl_va,
|
|
|
- virtual_addr &
|
|
|
- MMU_LARGE_PAGE_MASK);
|
|
|
- break;
|
|
|
-
|
|
|
- case HW_PAGE_SIZE1MB:
|
|
|
- case HW_MMU_COARSE_PAGE_SIZE:
|
|
|
- pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va,
|
|
|
- virtual_addr &
|
|
|
- MMU_SECTION_ADDR_MASK);
|
|
|
- break;
|
|
|
-
|
|
|
- case HW_PAGE_SIZE16MB:
|
|
|
- num_entries = 16;
|
|
|
- pte_addr = hw_mmu_pte_addr_l1(pg_tbl_va,
|
|
|
- virtual_addr &
|
|
|
- MMU_SSECTION_ADDR_MASK);
|
|
|
- break;
|
|
|
-
|
|
|
- default:
|
|
|
- return -EINVAL;
|
|
|
- }
|
|
|
-
|
|
|
- while (--num_entries >= 0)
|
|
|
- ((u32 *) pte_addr)[num_entries] = 0;
|
|
|
-
|
|
|
- return status;
|
|
|
-}
|
|
|
-
|
|
|
-/* mmu_flush_entry */
|
|
|
-static hw_status mmu_flush_entry(const void __iomem *base_address)
|
|
|
-{
|
|
|
- hw_status status = 0;
|
|
|
- u32 flush_entry_data = 0x1;
|
|
|
-
|
|
|
- /* write values to register */
|
|
|
- MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32(base_address, flush_entry_data);
|
|
|
-
|
|
|
- return status;
|
|
|
-}
|
|
|
-
|
|
|
-/* mmu_set_cam_entry */
|
|
|
-static hw_status mmu_set_cam_entry(const void __iomem *base_address,
|
|
|
- const u32 page_sz,
|
|
|
- const u32 preserved_bit,
|
|
|
- const u32 valid_bit,
|
|
|
- const u32 virtual_addr_tag)
|
|
|
-{
|
|
|
- hw_status status = 0;
|
|
|
- u32 mmu_cam_reg;
|
|
|
-
|
|
|
- mmu_cam_reg = (virtual_addr_tag << 12);
|
|
|
- mmu_cam_reg = (mmu_cam_reg) | (page_sz) | (valid_bit << 2) |
|
|
|
- (preserved_bit << 3);
|
|
|
-
|
|
|
- /* write values to register */
|
|
|
- MMUMMU_CAM_WRITE_REGISTER32(base_address, mmu_cam_reg);
|
|
|
-
|
|
|
- return status;
|
|
|
-}
|
|
|
-
|
|
|
-/* mmu_set_ram_entry */
|
|
|
-static hw_status mmu_set_ram_entry(const void __iomem *base_address,
|
|
|
- const u32 physical_addr,
|
|
|
- enum hw_endianism_t endianism,
|
|
|
- enum hw_element_size_t element_size,
|
|
|
- enum hw_mmu_mixed_size_t mixed_size)
|
|
|
-{
|
|
|
- hw_status status = 0;
|
|
|
- u32 mmu_ram_reg;
|
|
|
-
|
|
|
- mmu_ram_reg = (physical_addr & MMU_ADDR_MASK);
|
|
|
- mmu_ram_reg = (mmu_ram_reg) | ((endianism << 9) | (element_size << 7) |
|
|
|
- (mixed_size << 6));
|
|
|
-
|
|
|
- /* write values to register */
|
|
|
- MMUMMU_RAM_WRITE_REGISTER32(base_address, mmu_ram_reg);
|
|
|
-
|
|
|
- return status;
|
|
|
-
|
|
|
-}
|
|
|
-
|
|
|
-void hw_mmu_tlb_flush_all(const void __iomem *base)
|
|
|
-{
|
|
|
- __raw_writeb(1, base + MMU_GFLUSH);
|
|
|
-}
|
Fernando Guzman Lugo