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@@ -9182,11 +9182,14 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
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MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
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an_1000_val);
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- /* set 10 speed advertisement */
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+ /* set 100 speed advertisement */
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if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
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(phy->speed_cap_mask &
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- (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
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- PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
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+ (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
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+ PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) &&
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+ (phy->supported &
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+ (SUPPORTED_100baseT_Half |
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+ SUPPORTED_100baseT_Full)))) {
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an_10_100_val |= (1<<7);
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/* Enable autoneg and restart autoneg for legacy speeds */
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autoneg_val |= (1<<9 | 1<<12);
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@@ -9197,9 +9200,12 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
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}
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/* set 10 speed advertisement */
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if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
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- (phy->speed_cap_mask &
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- (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
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- PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
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+ (phy->speed_cap_mask &
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+ (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
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+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
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+ (phy->supported &
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+ (SUPPORTED_10baseT_Half |
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+ SUPPORTED_10baseT_Full)))) {
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an_10_100_val |= (1<<5);
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autoneg_val |= (1<<9 | 1<<12);
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if (phy->req_duplex == DUPLEX_FULL)
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@@ -9208,7 +9214,10 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
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}
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/* Only 10/100 are allowed to work in FORCE mode */
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- if (phy->req_line_speed == SPEED_100) {
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+ if ((phy->req_line_speed == SPEED_100) &&
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+ (phy->supported &
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+ (SUPPORTED_100baseT_Half |
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+ SUPPORTED_100baseT_Full))) {
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autoneg_val |= (1<<13);
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/* Enabled AUTO-MDIX when autoneg is disabled */
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bnx2x_cl45_write(bp, phy,
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@@ -9216,7 +9225,10 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
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(1<<15 | 1<<9 | 7<<0));
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DP(NETIF_MSG_LINK, "Setting 100M force\n");
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}
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- if (phy->req_line_speed == SPEED_10) {
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+ if ((phy->req_line_speed == SPEED_10) &&
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+ (phy->supported &
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+ (SUPPORTED_10baseT_Half |
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+ SUPPORTED_10baseT_Full))) {
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/* Enabled AUTO-MDIX when autoneg is disabled */
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bnx2x_cl45_write(bp, phy,
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MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
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@@ -9284,11 +9296,22 @@ static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
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struct link_vars *vars)
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{
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u32 idx;
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+ u32 pair_swap;
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u16 val;
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- u16 data = 0x01b1;
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+ u16 data;
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struct bnx2x *bp = params->bp;
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/* Do pair swap */
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+ /* Check for configuration. */
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+ pair_swap = REG_RD(bp, params->shmem_base +
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+ offsetof(struct shmem_region,
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+ dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
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+ PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
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+
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+ if (pair_swap == 0)
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+ return 0;
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+
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+ data = (u16)pair_swap;
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/* Write CMD_OPEN_OVERRIDE to STATUS reg */
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bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
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@@ -10787,9 +10810,7 @@ static struct bnx2x_phy phy_84833 = {
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.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
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.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
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.mdio_ctrl = 0,
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- .supported = (SUPPORTED_10baseT_Half |
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- SUPPORTED_10baseT_Full |
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- SUPPORTED_100baseT_Half |
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+ .supported = (SUPPORTED_100baseT_Half |
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SUPPORTED_100baseT_Full |
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SUPPORTED_1000baseT_Full |
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SUPPORTED_10000baseT_Full |
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