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@@ -42,29 +42,27 @@
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* Virtual to Physical Address mapping for IO devices.
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*/
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#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
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-#define AT91_VA_BASE_SPI AT91_IO_P2V(AT91RM9200_BASE_SPI)
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#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC)
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-#define AT91_VA_BASE_TWI AT91_IO_P2V(AT91RM9200_BASE_TWI)
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-#define AT91_VA_BASE_MCI AT91_IO_P2V(AT91RM9200_BASE_MCI)
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-#define AT91_VA_BASE_UDP AT91_IO_P2V(AT91RM9200_BASE_UDP)
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/* Internal SRAM is mapped below the IO devices */
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-#define AT91_SRAM_VIRT_BASE (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE)
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+#define AT91_SRAM_MAX SZ_1M
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+#define AT91_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_MAX)
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/* Serial ports */
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-#define ATMEL_MAX_UART 5 /* 4 USART3's and one DBGU port */
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-
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-/* FLASH */
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-#define AT91_FLASH_BASE 0x10000000 /* NCS0: Flash physical base address */
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+#define ATMEL_MAX_UART 7 /* 6 USART3's and one DBGU port (SAM9260) */
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+
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+/* External Memory Map */
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+#define AT91_CHIPSELECT_0 0x10000000
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+#define AT91_CHIPSELECT_1 0x20000000
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+#define AT91_CHIPSELECT_2 0x30000000
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+#define AT91_CHIPSELECT_3 0x40000000
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+#define AT91_CHIPSELECT_4 0x50000000
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+#define AT91_CHIPSELECT_5 0x60000000
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+#define AT91_CHIPSELECT_6 0x70000000
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+#define AT91_CHIPSELECT_7 0x80000000
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/* SDRAM */
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-#define AT91_SDRAM_BASE 0x20000000 /* NCS1: SDRAM physical base address */
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-
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-/* SmartMedia */
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-#define AT91_SMARTMEDIA_BASE 0x40000000 /* NCS3: Smartmedia physical base address */
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-
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-/* Compact Flash */
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-#define AT91_CF_BASE 0x50000000 /* NCS4-NCS6: Compact Flash physical base address */
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+#define AT91_SDRAM_BASE AT91_CHIPSELECT_1
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/* Clocks */
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#define AT91_SLOW_CLOCK 32768 /* slow clock */
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