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@@ -124,6 +124,11 @@ static unsigned long get_rate_gpt(struct clk *clk)
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return get_rate_per(5);
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return get_rate_per(5);
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}
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}
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+static unsigned long get_rate_lcdc(struct clk *clk)
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+{
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+ return get_rate_per(7);
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+}
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+
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static unsigned long get_rate_otg(struct clk *clk)
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static unsigned long get_rate_otg(struct clk *clk)
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{
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{
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return 48000000; /* FIXME */
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return 48000000; /* FIXME */
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@@ -167,6 +172,8 @@ DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL);
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DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL);
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+DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL);
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+DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk);
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DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
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DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
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DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
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DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
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DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
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DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
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@@ -183,6 +190,7 @@ DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL);
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DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL);
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DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
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DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
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DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1, 8, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1, 8, get_rate_ipg, NULL, NULL);
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+DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
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#define _REGISTER_CLOCK(d, n, c) \
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#define _REGISTER_CLOCK(d, n, c) \
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{ \
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{ \
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@@ -216,6 +224,7 @@ static struct clk_lookup lookups[] = {
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_REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk)
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_REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk)
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_REGISTER_CLOCK("fec.0", NULL, fec_clk)
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_REGISTER_CLOCK("fec.0", NULL, fec_clk)
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_REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
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_REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
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+ _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
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};
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};
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int __init mx25_clocks_init(void)
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int __init mx25_clocks_init(void)
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@@ -233,6 +242,9 @@ int __init mx25_clocks_init(void)
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__raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);
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__raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);
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__raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);
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__raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);
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+ /* Clock source for lcdc is upll */
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+ __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7), CRM_BASE + 0x64);
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+
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mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
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mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
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return 0;
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return 0;
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