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@@ -85,7 +85,7 @@ static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg,
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int i;
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int i;
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dprintk("R(%d):", reg & 0x7f);
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dprintk("R(%d):", reg & 0x7f);
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for (i = 0; i < count; i++)
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for (i = 0; i < count; i++)
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- printk(" %02x", buf[i]);
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+ printk(KERN_CONT " %02x", buf[i]);
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printk("\n");
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printk("\n");
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}
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}
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@@ -103,7 +103,7 @@ static int mt312_write(struct mt312_state *state, const enum mt312_reg_addr reg,
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int i;
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int i;
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dprintk("W(%d):", reg & 0x7f);
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dprintk("W(%d):", reg & 0x7f);
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for (i = 0; i < count; i++)
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for (i = 0; i < count; i++)
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- printk(" %02x", src[i]);
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+ printk(KERN_CONT " %02x", src[i]);
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printk("\n");
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printk("\n");
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}
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}
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@@ -744,7 +744,8 @@ static struct dvb_frontend_ops mt312_ops = {
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.type = FE_QPSK,
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.type = FE_QPSK,
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.frequency_min = 950000,
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.frequency_min = 950000,
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.frequency_max = 2150000,
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.frequency_max = 2150000,
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- .frequency_stepsize = (MT312_PLL_CLK / 1000) / 128, /* FIXME: adjust freq to real used xtal */
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+ /* FIXME: adjust freq to real used xtal */
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+ .frequency_stepsize = (MT312_PLL_CLK / 1000) / 128,
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.symbol_rate_min = MT312_SYS_CLK / 128, /* FIXME as above */
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.symbol_rate_min = MT312_SYS_CLK / 128, /* FIXME as above */
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.symbol_rate_max = MT312_SYS_CLK / 2,
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.symbol_rate_max = MT312_SYS_CLK / 2,
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.caps =
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.caps =
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