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@@ -79,7 +79,7 @@
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#define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
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#define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie) \
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- (((1<<cfg(trans)->base_params->num_of_queues) - 1) &\
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+ (((1<<trans->cfg->base_params->num_of_queues) - 1) &\
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(~(1<<(trans_pcie)->cmd_queue)))
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static int iwl_trans_rx_alloc(struct iwl_trans *trans)
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@@ -522,7 +522,7 @@ static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
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/* Tx queues */
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if (trans_pcie->txq) {
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for (txq_id = 0;
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- txq_id < cfg(trans)->base_params->num_of_queues; txq_id++)
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+ txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
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iwl_tx_queue_free(trans, txq_id);
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}
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@@ -547,7 +547,7 @@ static int iwl_trans_tx_alloc(struct iwl_trans *trans)
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int txq_id, slots_num;
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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- u16 scd_bc_tbls_size = cfg(trans)->base_params->num_of_queues *
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+ u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
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sizeof(struct iwlagn_scd_bc_tbl);
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/*It is not allowed to alloc twice, so warn when this happens.
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@@ -571,7 +571,7 @@ static int iwl_trans_tx_alloc(struct iwl_trans *trans)
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goto error;
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}
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- trans_pcie->txq = kcalloc(cfg(trans)->base_params->num_of_queues,
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+ trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
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sizeof(struct iwl_tx_queue), GFP_KERNEL);
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if (!trans_pcie->txq) {
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IWL_ERR(trans, "Not enough memory for txq\n");
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@@ -580,7 +580,7 @@ static int iwl_trans_tx_alloc(struct iwl_trans *trans)
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}
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/* Alloc and init all Tx queues, including the command queue (#4/#9) */
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- for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
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+ for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
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txq_id++) {
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slots_num = (txq_id == trans_pcie->cmd_queue) ?
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TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
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@@ -626,7 +626,7 @@ static int iwl_tx_init(struct iwl_trans *trans)
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spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
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/* Alloc and init all Tx queues, including the command queue (#4/#9) */
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- for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
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+ for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
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txq_id++) {
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slots_num = (txq_id == trans_pcie->cmd_queue) ?
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TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
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@@ -749,9 +749,9 @@ static int iwl_apm_init(struct iwl_trans *trans)
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iwl_apm_config(trans);
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/* Configure analog phase-lock-loop before activating to D0A */
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- if (cfg(trans)->base_params->pll_cfg_val)
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+ if (trans->cfg->base_params->pll_cfg_val)
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iwl_set_bit(trans, CSR_ANA_PLL_CFG,
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- cfg(trans)->base_params->pll_cfg_val);
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+ trans->cfg->base_params->pll_cfg_val);
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/*
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* Set "initialization complete" bit to move adapter from
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@@ -861,7 +861,7 @@ static int iwl_nic_init(struct iwl_trans *trans)
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if (iwl_tx_init(trans))
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return -ENOMEM;
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- if (cfg(trans)->base_params->shadow_reg_enable) {
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+ if (trans->cfg->base_params->shadow_reg_enable) {
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/* enable shadow regs in HW */
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iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
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0x800FFFFF);
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@@ -1080,7 +1080,7 @@ static void iwl_tx_start(struct iwl_trans *trans)
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iwl_write_targ_mem(trans, a, 0);
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for (; a < trans_pcie->scd_base_addr +
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SCD_TRANS_TBL_OFFSET_QUEUE(
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- cfg(trans)->base_params->num_of_queues);
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+ trans->cfg->base_params->num_of_queues);
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a += 4)
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iwl_write_targ_mem(trans, a, 0);
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@@ -1103,7 +1103,7 @@ static void iwl_tx_start(struct iwl_trans *trans)
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iwl_write_prph(trans, SCD_AGGR_SEL, 0);
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/* initiate the queues */
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- for (i = 0; i < cfg(trans)->base_params->num_of_queues; i++) {
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+ for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
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iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
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iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
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iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
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@@ -1120,7 +1120,7 @@ static void iwl_tx_start(struct iwl_trans *trans)
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}
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iwl_write_prph(trans, SCD_INTERRUPT_MASK,
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- IWL_MASK(0, cfg(trans)->base_params->num_of_queues));
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+ IWL_MASK(0, trans->cfg->base_params->num_of_queues));
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/* Activate all Tx DMA/FIFO channels */
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iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
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@@ -1188,7 +1188,7 @@ static int iwl_trans_tx_stop(struct iwl_trans *trans)
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}
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/* Unmap DMA from host system and free skb's */
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- for (txq_id = 0; txq_id < cfg(trans)->base_params->num_of_queues;
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+ for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
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txq_id++)
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iwl_tx_queue_unmap(trans, txq_id);
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@@ -1617,7 +1617,7 @@ static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
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int ret = 0;
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/* waiting for all the tx frames complete might take a while */
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- for (cnt = 0; cnt < cfg(trans)->base_params->num_of_queues; cnt++) {
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+ for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
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if (cnt == trans_pcie->cmd_queue)
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continue;
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txq = &trans_pcie->txq[cnt];
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@@ -1829,7 +1829,7 @@ static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
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int ret;
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size_t bufsz;
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- bufsz = sizeof(char) * 64 * cfg(trans)->base_params->num_of_queues;
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+ bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
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if (!trans_pcie->txq) {
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IWL_ERR(trans, "txq not ready\n");
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@@ -1839,7 +1839,7 @@ static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
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if (!buf)
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return -ENOMEM;
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- for (cnt = 0; cnt < cfg(trans)->base_params->num_of_queues; cnt++) {
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+ for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
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txq = &trans_pcie->txq[cnt];
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q = &txq->q;
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pos += scnprintf(buf + pos, bufsz - pos,
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@@ -2085,7 +2085,8 @@ const struct iwl_trans_ops trans_ops_pcie = {
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struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
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struct pci_dev *pdev,
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- const struct pci_device_id *ent)
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+ const struct pci_device_id *ent,
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+ const struct iwl_cfg *cfg)
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{
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struct iwl_trans_pcie *trans_pcie;
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struct iwl_trans *trans;
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@@ -2102,6 +2103,7 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
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trans->ops = &trans_ops_pcie;
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trans->shrd = shrd;
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+ trans->cfg = cfg;
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trans_pcie->trans = trans;
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spin_lock_init(&trans_pcie->irq_lock);
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init_waitqueue_head(&trans_pcie->ucode_write_waitq);
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