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@@ -1756,6 +1756,17 @@ static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
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else
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dev_err(&adapter->pdev->dev, "Invalid DCB "
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"configuration\n");
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+#ifdef IXGBE_FCOE
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+ if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
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+ struct ixgbe_ring_feature *f;
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+
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+ rx_ring = &adapter->rx_ring[queue0];
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+ f = &adapter->ring_feature[RING_F_FCOE];
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+ if ((queue0 == 0) && (index > rx_ring->reg_idx))
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+ queue0 = f->mask + index -
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+ rx_ring->reg_idx - 1;
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+ }
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+#endif /* IXGBE_FCOE */
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} else {
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queue0 = index;
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}
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@@ -2842,6 +2853,47 @@ static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
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return ret;
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}
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+#ifdef IXGBE_FCOE
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+/**
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+ * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
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+ * @adapter: board private structure to initialize
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+ *
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+ * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
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+ * The ring feature mask is not used as a mask for FCoE, as it can take any 8
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+ * rx queues out of the max number of rx queues, instead, it is used as the
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+ * index of the first rx queue used by FCoE.
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+ *
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+ **/
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+static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
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+{
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+ bool ret = false;
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+ struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
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+
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+ f->indices = min((int)num_online_cpus(), f->indices);
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+ if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
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+#ifdef CONFIG_IXGBE_DCB
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+ if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
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+ DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n");
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+ ixgbe_set_dcb_queues(adapter);
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+ }
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+#endif
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+ if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
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+ DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n");
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+ ixgbe_set_rss_queues(adapter);
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+ }
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+ /* adding FCoE rx rings to the end */
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+ f->mask = adapter->num_rx_queues;
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+ adapter->num_rx_queues += f->indices;
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+ if (adapter->num_tx_queues == 0)
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+ adapter->num_tx_queues = f->indices;
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+
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+ ret = true;
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+ }
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+
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+ return ret;
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+}
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+
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+#endif /* IXGBE_FCOE */
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/*
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* ixgbe_set_num_queues: Allocate queues for device, feature dependant
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* @adapter: board private structure to initialize
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@@ -2855,6 +2907,11 @@ static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
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**/
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static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
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{
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+#ifdef IXGBE_FCOE
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+ if (ixgbe_set_fcoe_queues(adapter))
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+ goto done;
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+
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+#endif /* IXGBE_FCOE */
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#ifdef CONFIG_IXGBE_DCB
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if (ixgbe_set_dcb_queues(adapter))
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goto done;
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@@ -3030,6 +3087,39 @@ static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
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}
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#endif
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+#ifdef IXGBE_FCOE
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+/**
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+ * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
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+ * @adapter: board private structure to initialize
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+ *
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+ * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
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+ *
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+ */
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+static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
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+{
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+ int i, fcoe_i = 0;
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+ bool ret = false;
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+ struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
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+
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+ if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
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+#ifdef CONFIG_IXGBE_DCB
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+ if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
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+ ixgbe_cache_ring_dcb(adapter);
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+ fcoe_i = adapter->rx_ring[0].reg_idx + 1;
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+ }
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+#endif /* CONFIG_IXGBE_DCB */
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+ if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
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+ ixgbe_cache_ring_rss(adapter);
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+ fcoe_i = f->mask;
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+ }
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+ for (i = 0; i < f->indices; i++, fcoe_i++)
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+ adapter->rx_ring[f->mask + i].reg_idx = fcoe_i;
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+ ret = true;
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+ }
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+ return ret;
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+}
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+
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+#endif /* IXGBE_FCOE */
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/**
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* ixgbe_cache_ring_register - Descriptor ring to register mapping
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* @adapter: board private structure to initialize
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@@ -3047,6 +3137,11 @@ static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
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adapter->rx_ring[0].reg_idx = 0;
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adapter->tx_ring[0].reg_idx = 0;
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+#ifdef IXGBE_FCOE
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+ if (ixgbe_cache_ring_fcoe(adapter))
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+ return;
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+
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+#endif /* IXGBE_FCOE */
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#ifdef CONFIG_IXGBE_DCB
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if (ixgbe_cache_ring_dcb(adapter))
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return;
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@@ -3420,6 +3515,7 @@ static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
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adapter->flags |= IXGBE_FLAG_RSC_ENABLED;
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#ifdef IXGBE_FCOE
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adapter->flags |= IXGBE_FLAG_FCOE_ENABLED;
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+ adapter->ring_feature[RING_F_FCOE].indices = IXGBE_FCRETA_SIZE;
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#endif /* IXGBE_FCOE */
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}
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