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+# EventClass.py
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+#
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+# This is a libray defining some events typs classes, which could
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+# be used by other scripts to analyzing the perf samples.
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+#
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+# Currently there are just a few classes defined for examples,
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+# PerfEvent is the base class for all perf event sample, PebsEvent
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+# is a HW base Intel x86 PEBS event, and user could add more SW/HW
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+# event classes based on requriements.
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+
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+import struct
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+
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+# Event types, user could add more here
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+EVTYPE_GENERIC = 0
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+EVTYPE_PEBS = 1 # Basic PEBS event
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+EVTYPE_PEBS_LL = 2 # PEBS event with load latency info
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+EVTYPE_IBS = 3
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+
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+#
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+# Currently we don't have good way to tell the event type, but by
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+# the size of raw buffer, raw PEBS event with load latency data's
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+# size is 176 bytes, while the pure PEBS event's size is 144 bytes.
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+#
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+def create_event(name, comm, dso, symbol, raw_buf):
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+ if (len(raw_buf) == 144):
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+ event = PebsEvent(name, comm, dso, symbol, raw_buf)
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+ elif (len(raw_buf) == 176):
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+ event = PebsNHM(name, comm, dso, symbol, raw_buf)
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+ else:
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+ event = PerfEvent(name, comm, dso, symbol, raw_buf)
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+
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+ return event
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+
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+class PerfEvent(object):
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+ event_num = 0
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+ def __init__(self, name, comm, dso, symbol, raw_buf, ev_type=EVTYPE_GENERIC):
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+ self.name = name
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+ self.comm = comm
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+ self.dso = dso
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+ self.symbol = symbol
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+ self.raw_buf = raw_buf
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+ self.ev_type = ev_type
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+ PerfEvent.event_num += 1
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+
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+ def show(self):
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+ print "PMU event: name=%12s, symbol=%24s, comm=%8s, dso=%12s" % (self.name, self.symbol, self.comm, self.dso)
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+
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+#
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+# Basic Intel PEBS (Precise Event-based Sampling) event, whose raw buffer
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+# contains the context info when that event happened: the EFLAGS and
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+# linear IP info, as well as all the registers.
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+#
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+class PebsEvent(PerfEvent):
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+ pebs_num = 0
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+ def __init__(self, name, comm, dso, symbol, raw_buf, ev_type=EVTYPE_PEBS):
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+ tmp_buf=raw_buf[0:80]
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+ flags, ip, ax, bx, cx, dx, si, di, bp, sp = struct.unpack('QQQQQQQQQQ', tmp_buf)
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+ self.flags = flags
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+ self.ip = ip
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+ self.ax = ax
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+ self.bx = bx
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+ self.cx = cx
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+ self.dx = dx
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+ self.si = si
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+ self.di = di
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+ self.bp = bp
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+ self.sp = sp
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+
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+ PerfEvent.__init__(self, name, comm, dso, symbol, raw_buf, ev_type)
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+ PebsEvent.pebs_num += 1
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+ del tmp_buf
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+
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+#
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+# Intel Nehalem and Westmere support PEBS plus Load Latency info which lie
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+# in the four 64 bit words write after the PEBS data:
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+# Status: records the IA32_PERF_GLOBAL_STATUS register value
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+# DLA: Data Linear Address (EIP)
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+# DSE: Data Source Encoding, where the latency happens, hit or miss
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+# in L1/L2/L3 or IO operations
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+# LAT: the actual latency in cycles
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+#
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+class PebsNHM(PebsEvent):
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+ pebs_nhm_num = 0
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+ def __init__(self, name, comm, dso, symbol, raw_buf, ev_type=EVTYPE_PEBS_LL):
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+ tmp_buf=raw_buf[144:176]
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+ status, dla, dse, lat = struct.unpack('QQQQ', tmp_buf)
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+ self.status = status
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+ self.dla = dla
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+ self.dse = dse
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+ self.lat = lat
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+
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+ PebsEvent.__init__(self, name, comm, dso, symbol, raw_buf, ev_type)
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+ PebsNHM.pebs_nhm_num += 1
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+ del tmp_buf
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