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@@ -80,6 +80,8 @@
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#define APMG_RFKILL_REG (APMG_BASE + 0x0014)
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#define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c)
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#define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020)
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+#define APMG_DIGITAL_SVR_REG (APMG_BASE + 0x0058)
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+#define APMG_ANALOG_SVR_REG (APMG_BASE + 0x006C)
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#define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
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#define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
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@@ -91,7 +93,8 @@
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#define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
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#define APMG_PS_CTRL_VAL_PWR_SRC_MAX (0x01000000) /* 3945 only */
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#define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
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-
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+#define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
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+#define APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
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#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
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