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@@ -480,6 +480,88 @@ static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
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}
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}
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}
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}
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+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
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+static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
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+{
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+ u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
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+
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+ b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
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+ if (core == 0) {
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+ b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
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+ b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
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+ } else {
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+ b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
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+ b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
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+ }
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+ b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
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+ b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
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+ b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
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+ b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
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+ b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
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+ b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
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+ b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
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+ b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
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+}
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+
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+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
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+static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
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+{
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+ u8 rxval, txval;
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+ u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
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+
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+ regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
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+ if (core == 0) {
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+ regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
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+ regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
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+ } else {
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+ regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
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+ regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
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+ }
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+ regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
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+ regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
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+ regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
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+ regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
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+ regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
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+ regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
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+ regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
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+ regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
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+
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+ b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
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+ b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
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+
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+ b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS,
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+ ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
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+ b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
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+ ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
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+ b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
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+ (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
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+ b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
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+ (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
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+
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+ if (core == 0) {
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+ b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
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+ b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
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+ } else {
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+ b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
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+ b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
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+ }
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+
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+ /* TODO: Call N PHY RF Ctrl Intc Override with 2, 0, 3 as arguments */
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+ /* TODO: Call N PHY RF Intc Override with 8, 0, 3, 0 as arguments */
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+ /* TODO: Call N PHY RF Seq with 0 as argument */
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+
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+ if (core == 0) {
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+ rxval = 1;
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+ txval = 8;
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+ } else {
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+ rxval = 4;
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+ txval = 2;
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+ }
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+
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+ /* TODO: Call N PHY RF Ctrl Intc Override with 1, rxval, (core + 1) */
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+ /* TODO: Call N PHY RF Ctrl Intc Override with 1, txval, (2 - core) */
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+}
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+
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/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
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/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
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static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
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static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
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{
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{
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