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@@ -68,8 +68,8 @@
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#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
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#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
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-#define MCFUART_BASE1 0x100 /* Base address of UART1 */
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-#define MCFUART_BASE2 0x140 /* Base address of UART2 */
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+#define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */
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+#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
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#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */
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#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */
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@@ -101,8 +101,8 @@
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#define MCF_IRQ_TIMER2 70 /* Timer 2 */
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#define MCF_IRQ_TIMER3 71 /* Timer 3 */
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#define MCF_IRQ_TIMER4 72 /* Timer 4 */
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-#define MCF_IRQ_UART1 73 /* UART 1 */
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-#define MCF_IRQ_UART2 74 /* UART 2 */
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+#define MCF_IRQ_UART0 73 /* UART 0 */
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+#define MCF_IRQ_UART1 74 /* UART 1 */
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#define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
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#define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */
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#define MCF_IRQ_USB0 77 /* USB Endpoint 0 */
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