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@@ -227,21 +227,21 @@ extern unsigned long ioremap_bot, ioremap_base;
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* doesn't support SMP. So we can use this as software bit, like
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* DIRTY.
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*
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- * PPC Book-E Linux implementation uses PPC HW PTE bit field definition,
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- * even it doesn't have HW PTE. 0-11th LSB of PTE stand for memory
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- * protection-related function. (See PTE structure in include/asm-ppc/mmu.h)
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- * Definition of _PAGE_XXX in "include/asm-ppc/pagetable.h" stands for
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- * above bits. Note that those bits values are CPU dependent, not
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- * architecture.
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+ * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
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+ * for memory protection related functions (see PTE structure in
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+ * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the
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+ * above bits. Note that the bit values are CPU specific, not architecture
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+ * specific.
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*
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- * Kernel PTE entry holds arch-dependent swp_entry structure under certain
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- * situation. In other words, in such situation, some portion of PTE bits
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- * are used as swp_entry. In PPC implementation, 3-24th LSB are shared with
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- * swp_entry, however 0-2nd three LSB still hold protection values.
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- * That means three protection bits are reserved for both PTE and SWAP
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- * entry at the most three LSBs.
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+ * The kernel PTE entry holds an arch-dependent swp_entry structure under
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+ * certain situations. In other words, in such situations some portion of
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+ * the PTE bits are used as a swp_entry. In the PPC implementation, the
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+ * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
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+ * hold protection values. That means the three protection bits are
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+ * reserved for both PTE and SWAP entry at the most significant three
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+ * LSBs.
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*
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- * There are three protection bits available for SWAP entry;
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+ * There are three protection bits available for SWAP entry:
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* _PAGE_PRESENT
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* _PAGE_FILE
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* _PAGE_HASHPTE (if HW has)
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