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@@ -99,7 +99,7 @@ ENTRY(__hyp_stub_install_secondary)
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* immediately.
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*/
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compare_cpu_mode_with_primary r4, r5, r6, r7
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- bxne lr
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+ movne pc, lr
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/*
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* Once we have given up on one CPU, we do not try to install the
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@@ -111,7 +111,7 @@ ENTRY(__hyp_stub_install_secondary)
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*/
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cmp r4, #HYP_MODE
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- bxne lr @ give up if the CPU is not in HYP mode
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+ movne pc, lr @ give up if the CPU is not in HYP mode
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/*
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* Configure HSCTLR to set correct exception endianness/instruction set
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@@ -120,7 +120,8 @@ ENTRY(__hyp_stub_install_secondary)
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* Eventually, CPU-specific code might be needed -- assume not for now
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*
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* This code relies on the "eret" instruction to synchronize the
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- * various coprocessor accesses.
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+ * various coprocessor accesses. This is done when we switch to SVC
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+ * (see safe_svcmode_maskall).
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*/
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@ Now install the hypervisor stub:
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adr r7, __hyp_stub_vectors
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@@ -155,14 +156,7 @@ THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE
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1:
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#endif
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- bic r7, r4, #MODE_MASK
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- orr r7, r7, #SVC_MODE
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-THUMB( orr r7, r7, #PSR_T_BIT )
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- msr spsr_cxsf, r7 @ This is SPSR_hyp.
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-
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- __MSR_ELR_HYP(14) @ msr elr_hyp, lr
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- __ERET @ return, switching to SVC mode
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- @ The boot CPU mode is left in r4.
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+ bx lr @ The boot CPU mode is left in r4.
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ENDPROC(__hyp_stub_install_secondary)
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__hyp_stub_do_trap:
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@@ -200,7 +194,7 @@ ENDPROC(__hyp_get_vectors)
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@ fall through
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ENTRY(__hyp_set_vectors)
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__HVC(0)
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- bx lr
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+ mov pc, lr
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ENDPROC(__hyp_set_vectors)
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#ifndef ZIMAGE
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