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@@ -385,15 +385,15 @@ BEGIN_FTR_SECTION
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oris r0,r6,(SLB_ESID_V)@h
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oris r0,r6,(SLB_ESID_V)@h
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ori r0,r0,(SLB_NUM_BOLTED-1)@l
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ori r0,r0,(SLB_NUM_BOLTED-1)@l
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- /* Update the last bolted SLB */
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+ /* Update the last bolted SLB. No write barriers are needed
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+ * here, provided we only update the current CPU's SLB shadow
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+ * buffer.
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+ */
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ld r9,PACA_SLBSHADOWPTR(r13)
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ld r9,PACA_SLBSHADOWPTR(r13)
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li r12,0
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li r12,0
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std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
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std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
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- eieio
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std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */
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std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */
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- eieio
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std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */
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std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */
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- eieio
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slbie r6
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slbie r6
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slbie r6 /* Workaround POWER5 < DD2.1 issue */
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slbie r6 /* Workaround POWER5 < DD2.1 issue */
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